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stm8s903k3 stm8s903f3 16 mhz stm8s 8-bit mcu, up to 8 kbytes flash, 1 kbyte ram, 640 bytes eeprom,10-bit adc, 2 timers, uart, spi, i2c features core ? 16 mhz advanced stm8 core with harvard architecture and 3-stage pipeline ? extended instruction set memories ? program memory: 8 kbytes flash; data retention 20 years at 55 c after 10 kcycles ? data memory: 640 bytes true data eeprom; endurance 300 kcycles ? ram: 1 kbytes clock, reset and supply management ? 2.95 to 5.5 v operating voltage ? flexible clock control, 4 master clock sources: - low power crystal resonator oscillator - external clock input - internal, user-trimmable 16 mhz rc - internal low power 128 khz rc ? clock security system with clock monitor ? power management: - low power modes (wait, active-halt, halt) - switch-off peripheral clocks individually ? permanently active, low consumption power-on and power-down reset interrupt management ? nested interrupt controller with 32 interrupts ? up to 28 external interrupts on 7 vectors timers ? advanced control timer: 16-bit, 4 capcom channels, 3 complementary outputs, dead-time insertion and flexible synchronization ? 16-bit general purpose timer, with 3 capcom channels (ic, oc or pwm) ? 8-bit basic timer with 8-bit prescaler ? auto wakeup timer ? window and independent watchdog timers communications interfaces ? uart with clock output for synchronous operation, smartcard, irda, lin master mode ? spi interface up to 8 mbit/s ? i 2 c interface up to 400 kbit/s analog to digital converter (adc) ? 10-bit, 1 lsb adc with up to 7 muxed channels + 1 internal channel, scan mode and analog watchdog ? internal reference voltage measurement i/os ? up to 28 i/os on a 32-pin package including 21 high sink outputs ? highly robust i/o design, immune against current injection development support ? embedded single wire interface module (swim) for fast on-chip programming and non intrusive debugging unique id: 96-bit key including lot number 1/116 docid15590 rev 8 june 2012 www.st.com ufqfpn32 5x5 lqfp32 7x7 sdip32 400 mils tssop20 so20w 300 mils ufqfpn20 3x3
contents 1 introduction ..............................................................................................................8 2 description ...............................................................................................................9 3 block diagram ........................................................................................................10 4 product overview ...................................................................................................11 4.1 central processing unit stm8 .....................................................................................11 4.2 single wire interface module (swim) and debug module (dm) ..................................11 4.3 interrupt controller .......................................................................................................12 4.4 flash program and data eeprom memory ................................................................12 4.5 clock controller ............................................................................................................13 4.6 power management ....................................................................................................14 4.7 watchdog timers ..........................................................................................................14 4.8 auto wakeup counter ...................................................................................................15 4.9 beeper ........................................................................................................................15 4.10 tim1 - 16-bit advanced control timer .........................................................................15 4.11 tim5 - 16-bit general purpose timer ..........................................................................16 4.12 tim6 - 8-bit basic timer ..............................................................................................16 4.13 analog-to-digital converter (adc1) ............................................................................16 4.14 communication interfaces .........................................................................................17 4.14.1 uart1 ...............................................................................................17 4.14.2 spi .....................................................................................................18 4.14.3 i2c ......................................................................................................18 5 pinout and pin description ...................................................................................19 5.1 stm8s903f3 tssop20/so20 pinout ........................................................................20 5.2 stm8s903f3 ufqfpn20 pinout ................................................................................21 5.3 tssop/so/ufqfpn20 pin description ......................................................................22 5.4 stm8s903k3 ufqfpn32/lqfp32/sdip32 pinout ....................................................23 5.5 ufqfpn/lqfp/sdip32 pin description ......................................................................24 5.6 alternate function remapping .......................................................................................26 6 memory and register map .....................................................................................27 6.1 memory map ................................................................................................................27 6.2 register map ...............................................................................................................28 6.2.1 i/o port hardware register map ............................................................28 6.2.2 general hardware register map ...........................................................29 6.2.3 cpu/swim/debug module/interrupt controller registers .....................38 7 interrupt vector mapping ......................................................................................41 8 option bytes ...........................................................................................................43 8.1 stm8s903k3/f3 alternate function remapping bits ....................................................45 docid15590 rev 8 2/116 stm8s903k3 stm8s903f3 contents
9 unique id ................................................................................................................49 10 electrical characteristics ....................................................................................50 10.1 parameter conditions .................................................................................................50 10.1.1 minimum and maximum values .........................................................50 10.1.2 typical values .....................................................................................50 10.1.3 typical curves ....................................................................................50 10.1.4 loading capacitor ...............................................................................50 10.1.5 pin input voltage .................................................................................50 10.2 absolute maximum ratings ........................................................................................51 10.3 operating conditions ..................................................................................................53 10.3.1 vcap external capacitor ....................................................................54 10.3.2 supply current characteristics ............................................................55 10.3.3 external clock sources and timing characteristics .............................65 10.3.4 internal clock sources and timing characteristics ...............................67 10.3.5 memory characteristics ......................................................................69 10.3.6 i/o port pin characteristics .................................................................70 10.3.7 reset pin characteristics ....................................................................78 10.3.8 spi serial peripheral interface ............................................................81 10.3.9 i 2 c interface characteristics ...............................................................84 10.3.10 10-bit adc characteristics ................................................................85 10.3.11 emc characteristics .........................................................................89 11 package information ............................................................................................92 11.1 32-pin lqfp package mechanical data .....................................................................92 11.2 32-lead ufqfpn package mechanical data .............................................................94 11.3 20-lead ufqfpn package mechanical data .............................................................95 11.4 ufqfpn recommended footprint ..............................................................................97 11.5 sdip32 package mechanical data .............................................................................98 11.6 20-pin tssop package mechanical data ................................................................100 11.7 20-pin so package mechanical data .......................................................................101 11.8 thermal characteristics ............................................................................................102 11.8.1 reference document ........................................................................103 11.8.2 selecting the product temperature range .........................................103 12 ordering information .........................................................................................104 12.1 stm8s903k3/f3 fastrom microcontroller option list ..........................................104 13 stm8 development tools ..................................................................................110 13.1 emulation and in-circuit debugging tools .................................................................110 13.2 software tools ..........................................................................................................110 13.2.1 stm8 toolset ....................................................................................111 13.2.2 c and assembly toolchains ..............................................................111 13.3 programming tools ..................................................................................................111 14 revision history .................................................................................................112 3/116 docid15590 rev 8 contents stm8s903k3 stm8s903f3
list of tables table 1. stm8s903k3/f3 access line features .......................................................................................9 table 2. peripheral clock gating bit assignments in clk_pckenr1/2 registers ..................................14 table 3. tim timer features ....................................................................................................................16 table 4. legend/abbreviations for pinout tables ...................................................................................19 table 5. tssop20/so20/ufqfpn20 pin description ...........................................................................24 table 6. ufqfpn32/lqfp32/sdip32 pin description ...........................................................................24 table 7. i/o port hardware register map ................................................................................................28 table 8. general hardware register map ................................................................................................43 table 9. cpu/swim/debug module/interrupt controller registers .........................................................54 table 10. interrupt mapping ...................................................................................................................41 table 11. option bytes .........................................................................................................................112 table 12. option byte description ...........................................................................................................43 table 13. stm8s903k3 alternate function remapping bits [7:2] for 32-pin packages ...........................45 table 14. stm8s903f3 alternate function remapping bits [7:2] for 20-pin packages ...........................46 table 15. stm8s903k3 alternate function remapping bits [1:0] for 32-pin packages .........................102 table 16. stm8s903f3 alternate function remapping bits [1:0] for 20-pin packages ...........................48 table 17. unique id registers (96 bits) .................................................................................................112 table 18. voltage characteristics ...........................................................................................................51 table 19. current characteristics ...........................................................................................................51 table 20. thermal characteristics ..........................................................................................................52 table 21. general operating conditions .................................................................................................53 table 22. operating conditions at power-up/power-down ......................................................................54 table 23. total current consumption with code execution in run mode at v dd = 5 v .............................55 table 24. total current consumption with code execution in run mode at v dd = 3.3 v ..........................56 table 25. total current consumption in wait mode at v dd = 5 v ............................................................57 table 26. total current consumption in wait mode at v dd = 3.3 v .........................................................57 table 27. total current consumption in active halt mode at v dd = 5 v ..................................................58 table 28. total current consumption in active halt mode at v dd = 3.3 v ...............................................59 table 29. total current consumption in halt mode at v dd = 5 v .............................................................60 table 30. total current consumption in halt mode at v dd = 3.3 v ..........................................................60 table 31. wakeup times .........................................................................................................................60 table 32. total current consumption and timing in forced reset state ....................................................61 table 33. peripheral current consumption .............................................................................................62 table 34. hse user external clock characteristics .................................................................................65 table 35. hse oscillator characteristics .................................................................................................65 table 36. hsi oscillator characteristics ..................................................................................................67 table 37. lsi oscillator characteristics ...................................................................................................68 table 38. ram and hardware registers ..................................................................................................69 table 39. flash program memory/data eeprom memory ....................................................................69 table 40. i/o static characteristics .........................................................................................................70 table 41. output driving current (standard ports) ..................................................................................72 table 42. output driving current (true open drain ports) ........................................................................73 table 43. output driving current (high sink ports) ..................................................................................73 table 44. nrst pin characteristics ........................................................................................................78 table 45. spi characteristics ..................................................................................................................81 table 46. i 2 c characteristics ..................................................................................................................84 table 47. adc characteristics ................................................................................................................85 docid15590 rev 8 4/116 stm8s903k3 stm8s903f3 list of tables
table 48. adc accuracy with r ain < 10 k , v dd = 5 v .........................................................................86 table 49. adc accuracy with r ain < 10 k r ain , v dd = 3.3 v ..............................................................87 table 50. ems data ................................................................................................................................89 table 51. emi data .................................................................................................................................90 table 52. esd absolute maximum ratings .............................................................................................91 table 53. electrical sensitivities .............................................................................................................91 table 54. 32-pin low profile quad flat package mechanical data .........................................................102 table 55. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data .............................94 table 56. 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data ....96 table 57. 32-lead shrink plastic dip (400 ml) package mechanical data ..............................................99 table 58. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data .......................................................101 table 59. 20-lead, plastic small outline (300 mils) mechanical data ....................................................101 table 60. thermal characteristics ........................................................................................................102 table 61. document revision history ....................................................................................................112 5/116 docid15590 rev 8 list of tables stm8s903k3 stm8s903f3
list of figures figure 1. block diagram .........................................................................................................................10 figure 2. flash memory organization ....................................................................................................13 figure 3. stm8s903f3 tssop20/so20 pinout ...................................................................................23 figure 4. stm8s903f3 ufqfpn20 pinout ...........................................................................................23 figure 5. stm8s903k3 ufqfpn32/lqfp32 pinout ............................................................................23 figure 6. stm8s903k3 sdip32 pinout .................................................................................................24 figure 7. memory map ...........................................................................................................................27 figure 8. pin loading conditions .............................................................................................................50 figure 9. pin input voltage .....................................................................................................................51 figure 10. f cpumax versus v dd .............................................................................................................. 54 figure 11. external capacitor c ext ....................................................................................................... 55 figure 12. typ i dd(run) vs. v dd hse user external clock, f cpu = 16 mhz .............................................62 figure 13. typ i dd(run) vs. f cpu hse user external clock, v dd = 5 v ....................................................63 figure 14. typ i dd(run) vs. v dd hsi rc osc, f cpu = 16 mhz .................................................................63 figure 15. typ i dd(wfi) vs. v dd hse user external clock, f cpu = 16 mhz ..............................................64 figure 16. typ i dd(wfi) vs. f cpu hse user external clock, v dd = 5 v .....................................................64 figure 17. typ i dd(wfi) vs. v dd hsi rc osc, f cpu = 16 mhz .................................................................64 figure 18. hse external clocksource .....................................................................................................65 figure 19. hse oscillator circuit diagram ...............................................................................................66 figure 20. typical hsi frequency variation vs v dd @ 4 temperatures ..................................................68 figure 21. typical lsi frequency variation vs v dd @ 4 temperatures ...................................................68 figure 22. typical v il and v ih vs v dd @ 4 temperatures ......................................................................71 figure 23. typical pull-up resistance vs v dd @ 4 temperatures ............................................................72 figure 24. typical pull-up current vs v dd @ 4 temperatures .................................................................72 figure 25. typ. v ol @ v dd = 5 v (standard ports) ................................................................................74 figure 26. typ. v ol @ v dd = 3.3 v (standard ports) .............................................................................74 figure 27. typ. v ol @ v dd = 5 v (true open drain ports) ......................................................................75 figure 28. typ. v ol @ v dd = 3.3 v (true open drain ports) ...................................................................75 figure 29. typ. v ol @ v dd = 5 v (high sink ports) ................................................................................76 figure 30. typ. v ol @ v dd = 3.3 v (high sink ports) .............................................................................76 figure 31. typ. v dd - v oh @ v dd = 5 v (standard ports) .......................................................................77 figure 32. typ. v dd - v oh @ v dd = 3.3 v (standard ports) ...................................................................77 figure 33. typ. v dd - v oh @ v dd = 5 v (high sink ports) .......................................................................78 figure 34. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) ....................................................................78 figure 35. typical nrst v il and v ih vs v dd @ 4 temperatures ...........................................................79 figure 36. typical nrst pull-up resistance vs v dd @ 4 temperatures .................................................80 figure 37. typical nrst pull-up current vs v dd @ 4 temperatures ......................................................80 figure 38. recommended reset pin protection ......................................................................................81 figure 39. spi timing diagram - slave mode and cpha = 0 ..................................................................83 figure 40. spi timing diagram - slave mode and cpha = 1 ..................................................................83 figure 41. spi timing diagram - master mode (1) ................................................................................... 84 figure 42. typical application with i 2 c bus and timing diagram ............................................................85 figure 43. adc accuracy characteristics ...............................................................................................88 figure 44. typical application with adc ................................................................................................88 figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................92 figure 46. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ............................................94 figure 47. 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) ................................95 docid15590 rev 8 6/116 stm8s903k3 stm8s903f3 list of figures
figure 48. recommended footprint for on-board emulation ..................................................................97 figure 49. recommended footprint without on-board emulation ...........................................................98 figure 50. 32-lead shrink plastic dip (400 ml) package ........................................................................98 figure 51. 20-pin, 4.40 mm body, 0.65 mm pitch .................................................................................101 figure 52. 20-lead, plastic small outline (300 mils) package ...............................................................101 figure 53. stm8s903k3/f3 ordering information scheme ..................................................................104 7/116 docid15590 rev 8 list of figures stm8s903k3 stm8s903f3
introduction 1 this datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. ? for complete information on the stm8s microcontroller memory, registers and peripherals, please refer to the stm8s microcontroller family reference manual (rm0016). ? for information on programming, erasing and protection of the internal flash memory please refer to the stm8s flash programming manual (pm0051). ? for information on the debug and swim (single wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). ? for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044). docid15590 rev 8 8/116 stm8s903k3 stm8s903f3 introduction
description 2 the stm8s903k3 and stm8s903f3 8-bit microcontrollers offer 8 kbytes flash program memory, plus integrated true data eeprom. the stm8s microcontroller family reference manual (rm0016) refers to devices in this family as low-density. they provide the following benefits: performance, robustness, and reduced system cost. device performance and robustness are ensured by advanced core and peripherals made in a state-of-the art technology, a 16 mhz clock frequency, robust i/os, independent watchdogs with separate clock source, and a clock security system. the system cost is reduced thanks to an integrated true data eeprom for up to 300 kwrite/erase cycles and a high system integration level with internal clock oscillators, watchdog and brown-out reset. full documentation is offered as well as a wide choice of development tools. table 1: stm8s903k3/f3 access line features stm8s903f3 stm8s903k3 device 20 32 pin count 16 (2) 28 (1) max. number of gpios (i/os) 16 28 ext. interrupt pins 7 timer capcom channels 2 3 timer complementary outputs 5 7 a/d converter channels 12 21 high sink i/os 8k low density flash program memory(bytes) 640 (3) data eeprom (bytes) 1k ram (bytes) multipurpose timer (tim1), spi, i 2 c, uart window wdg, independent wdg, adc, pwm timer (tim5), 8-bit timer (tim6) peripheral set (1) including 21 high sink outputs (2) including 12 high sink outputs (3) no read-while-write (rww) capability 9/116 docid15590 rev 8 description stm8s903k3 stm8s903f3
block diagram 3 figure 1: block diagram docid15590 rev 8 10/116 stm8s903k3 stm8s903f3 block diagram xt al 1-16 mhz rc int. 16 mhz rc int. 128 khz stm8 core deb ug/swim i 2 c spi u ar t1 16-bit gener al pur pose a wu timer reset b loc k reset por bor cloc k controller detector cloc k to per ipher als and core 8 mbit/s lin master address and data b us windo w wdg 8 kb ytes 640 b ytes 1 kb ytes adc1 4 capcom reset 400 kbit/s single wire deb ug interf . spi em ul. channels prog r am flash 16-bit adv anced control timer (tim1) 8-bit basic timer data eepr om ram up to beeper 1/2/4 khz beep independent wdg (tim6) 3 capcom channels up to + 3 complementar y outputs timer (tim5) up to 7 channels
product overview 4 the following section intends to give an overview of the basic features of the device functional modules and peripherals. for more detailed information please refer to the corresponding family reference manual (rm0016). central processing unit stm8 4.1 the 8-bit stm8 core is designed for code efficiency and performance. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. architecture and registers ? harvard architecture ? 3-stage pipeline ? 32-bit wide program memory bus - single cycle fetching for most instructions ? x and y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations ? 8-bit accumulator ? 24-bit program counter - 16-mbyte linear memory space ? 16-bit stack pointer - access to a 64 k-level stack ? 8-bit condition code register - 7 condition flags for the result of the last instruction addressing ? 20 addressing modes ? indexed indirect addressing mode for look-up tables located anywhere in the address space ? stack pointer relative addressing mode for local variables and parameter passing instruction set ? 80 instructions with 2-byte average instruction size ? standard data movement and logic/arithmetic functions ? 8-bit by 8-bit multiplication ? 16-bit by 8-bit and 16-bit by 16-bit division ? bit manipulation ? data transfer between stack and accumulator (push/pop) with direct stack access ? data transfer using the x and y registers or direct memory-to-memory transfers single wire interface module (swim) and debug module (dm) 4.2 the single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming. 11/116 docid15590 rev 8 product overview stm8s903k3 stm8s903f3
swim single wire interface module for direct access to the debug module and memory programming. the interface can be activated in all device operation modes. the maximum data transmission speed is 145 bytes/ms. debug module the non-intrusive debugging module features a performance close to a full-featured emulator. beside memory and peripherals, also cpu operation can be monitored in real-time by means of shadow registers. ? r/w to ram and peripheral registers in real-time ? r/w access to all resources by stalling the cpu ? breakpoints on all program-memory instructions (software breakpoints) ? two advanced breakpoints, 23 predefined configurations interrupt controller 4.3 ? nested interrupts with three software priority levels ? 32 interrupt vectors with hardware priority ? up to 28 external interrupts on 7 vectors including tli ? trap and reset interrupts flash program and data eeprom memory 4.4 ? 8 kbytes of flash program single voltage flash memory ? 640 bytes true data eeprom ? user option byte area write protection (wp) write protection of flash program memory and data eeprom is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. there are two levels of write protection. the first level is known as mass (memory access security system). mass is always enabled and protects the main flash program memory, data eeprom and option bytes. to perform in-application programming (iap), this write protection can be removed by writing a mass key sequence in a control register. this allows the application to write to data eeprom, modify the contents of main program memory or the device option bytes. a second level of write protection, can be enabled to further protect a specific area of memory known as ubc (user boot code). refer to the figure below. the size of the ubc is programmable through the ubc option byte, in increments of 1 page (64-byte block) by programming the ubc option byte in icp mode. this divides the program memory into two areas: ? main program memory: up to 8 kbytes minus ubc ? user-specific boot code (ubc): configurable up to 8 kbytes the ubc area remains write-protected during in-application programming. this means that the mass keys do not unlock the ubc area. it protects the memory used to store the boot docid15590 rev 8 12/116 stm8s903k3 stm8s903f3 product overview
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the iap and communication routines. figure 2: flash memory organization read-out protection (rop) the read-out protection blocks reading and writing the flash program memory and data eeprom memory in icp mode (and debug mode). once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. clock controller 4.5 the clock controller distributes the system clock (f master ) coming from different oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features ? clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler. ? safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. the clock signal is not switched until the new clock source is ready. the design guarantees glitch-free switching. ? clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ? master clock sources: four different clock sources can be used to drive the master clock: - 1-16 mhz high-speed external crystal (hse) 13/116 docid15590 rev 8 product overview stm8s903k3 stm8s903f3 ubc area prog r am memor y area data memor y area ( 640 b ytes) remains wr ite protected dur ing iap data eepr om memor y wr ite access possib le f or iap option b ytes prog r ammab le b ytes (1 page) up to 8 kb ytes (in 1 page steps) area from 64 ? lo w density flash prog r am memor y (8 kb ytes)
- up to 16 mhz high-speed user-external clock (hse user-ext) - 16 mhz high-speed internal rc oscillator (hsi) - 128 khz low-speed internal rc (lsi) ? startup clock: after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css): this feature can be enabled by software. if an hse clock failure occurs, the internal rc (16 mhz/8) is automatically selected by the css and an interrupt can optionally be generated. ? configurable main clock output (cco): this outputs an external clock for use by the application. table 2: peripheral clock gating bit assignments in clk_pckenr1/2 registers peripheral clock bit peripheral clock bit peripheral clock bit peripheral clock bit adc cken23 reserved pcken27 uart1 pcken13 tim1 pcken17 awu pcken22 reserved pcken26 reserved pcken12 im5 pcken16 reserved pcken21 reserved pcken25 spi pcken11 reserved pcken15 reserved pcken20 reserved pcken24 i 2 c pcken10 tim6 pcken14 power management 4.6 for efficent power management, the application can be put in one of four different low-power modes. you can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. ? wait mode: in this mode, the cpu is stopped, but peripherals are kept running. the wakeup is performed by an internal or external interrupt or reset. ? active halt mode with regulator on: in this mode, the cpu and peripheral clocks are stopped. an internal wakeup is generated at programmable intervals by the auto wake up unit (awu). the main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. wakeup is triggered by the internal awu interrupt, external interrupt or reset. ? active halt mode with regulator off: this mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower. ? halt mode: in this mode the microcontroller uses the least power. the cpu and peripheral clocks are stopped, the main voltage regulator is powered off. wakeup is triggered by external event or reset. watchdog timers 4.7 the watchdog system is based on two independent timers providing maximum security to the applications. docid15590 rev 8 14/116 stm8s903k3 stm8s903f3 product overview
activation of the watchdog timers is controlled by option bytes or by software. once activated, the watchdogs cannot be disabled by the user program without performing a reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application perfectly. the application software must refresh the counter before time-out and during a limited time window. a reset is generated in two situations: 1. timeout: at 16 mhz cpu clock the time-out period can be adjusted between 75 s up to 64 ms. 2. refresh out of window: the downcounter is refreshed before its value is lower than the one stored in the window register. independent watchdog timer the independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc clock source, and thus stays active even in case of a cpu clock failure the iwdg time base spans from 60 s to 1 s. auto wakeup counter 4.8 ? used for auto wakeup from active halt mode ? clock source: internal 128 khz internal low frequency rc oscillator or external clock ? lsi clock can be internally connected to tim1 input capture channel 1 for calibration beeper 4.9 the beeper function outputs a signal on the beep pin for sound generation. the signal is in the range of 1, 2 or 4 khz. the beeper output port is only available through the alternate function remap option bit afr7. tim1 - 16-bit advanced control timer 4.10 this is a high-end timer designed for a wide range of control applications. with its complementary outputs, dead-time control and center-aligned pwm capability, the field of applications is extended to motor control, lighting and half-bridge driver ? 16-bit up, down and up/down autoreload counter with 16-bit prescaler ? four independent capture/compare channels (capcom) configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output 15/116 docid15590 rev 8 product overview stm8s903k3 stm8s903f3
? synchronization module to control the timer with external signals or to synchronise with tim5 or tim6 ? break input to force the timer outputs into a defined state ? three complementary outputs with adjustable dead time ? encoder mode ? interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break tim5 - 16-bit general purpose timer 4.11 ? 16-bit autoreload (ar) up-counter ? 15-bit prescaler adjustable to fixed power of 2 ratios 132768 ? 3 individually configurable capture/compare channels ? pwm mode ? interrupt sources: 3 x input capture/output compare, 1 x overflow/update ? synchronization module to control the timer with external signals or to synchronize with tim1 or tim6 tim6 - 8-bit basic timer 4.12 ? 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 ? clock source: cpu clock ? interrupt source: 1 x overflow/update ? synchronization module to control the timer with external signals or to synchronize with tim1 or tim5. table 3: tim timer features timer synchronization/ chaining ext. trigger complementary outputs capcom channels counting mode prescaler counter size (bits) timer yesyes 3 4 up/down any integer from 1 to 65536 16tim1 no 0 3 up any power of 2 from 1 to 32768 16tim5 no 0 0 up any power of 2 from 1 to 128 8tim6 analog-to-digital converter (adc1) 4.13 the stm8s903k3 family products contain a 10-bit successive approximation a/d converter (adc1) with up to 7 external and 1 internal multiplexed input channels and the following main features: ? input voltage range: 0 to v dd docid15590 rev 8 16/116 stm8s903k3 stm8s903f3 product overview
? conversion time: 14 clock cycles ? single and continuous and buffered continuous conversion modes ? buffer size (n x 10 bits) where n = number of input channels ? scan mode for single and continuous conversion of a sequence of channels ? analog watchdog capability with programmable upper and lower thresholds ? internal reference voltage on channel ain7 ? analog watchdog interrupt ? external trigger input ? trigger from tim1 trgo ? end of conversion (eoc) interrupt internal bandgap reference voltage channel ain7 is internally connected to the internal bandgap reference voltage. the internal bandgap reference is constant and can be used, for example, to monitor v dd . it is independent of variations in v dd and ambient temperature t a . communication interfaces 4.14 the following communication interfaces are implemented: ? uart1: full feature uart, synchronous mode, spi master mode, smartcard mode, irda mode, single wire mode, lin2.1 master capability ? spi : full and half-duplex, 8 mbit/s ? i2c: up to 400 kbit/s uart1 4.14.1 main features ? one mbit/s full duplex sci ? spi emulation ? high precision baud rate generator ? smartcard emulation ? irda sir encoder decoder ? lin master mode ? single wire half duplex mode asynchronous communication (uart mode) ? full duplex communication - nrz standard format (mark/space) ? programmable transmit and receive baud rates up to 1 mbit/s (f cpu /16) and capable of following any standard baud rate regardless of the input frequency ? separate enable bits for transmitter and receiver ? two receiver wakeup modes: - address bit (msb) - idle line (interrupt) 17/116 docid15590 rev 8 product overview stm8s903k3 stm8s903f3
? transmission error detection with interrupt generation ? parity control synchronous communication ? full duplex synchronous transfers ? spi master operation ? 8-bit data communication ? maximum speed: 1 mbit/s at 16 mhz (f cpu /16) lin master mode ? emission: generates 13-bit synch break frame ? reception: detects 11-bit break frame spi 4.14.2 ? maximum speed: 8 mbit/s (f master /2) both for master and slave ? full duplex synchronous transfers ? simplex synchronous transfers on two lines with a possible bidirectional data line ? master or slave operation - selectable by hardware or software ? crc calculation ? 1 byte tx and rx buffer ? slave/master selection input pin i2c 4.14.3 ? i2c master features: - clock generation - start and stop generation ? i2c slave features: - programmable i2c address detection - stop bit detection ? generation and detection of 7-bit/10-bit addressing and general call ? supports different communication speeds: - standard speed (up to 100 khz) - fast speed (up to 400 khz) docid15590 rev 8 18/116 stm8s903k3 stm8s903f3 product overview
pinout and pin description 5 table 4: legend/abbreviations for pinout tables i= input, o = output, s = power supply type cm = cmos input level hs = high sink output o1 = slow (up to 2 mhz) output speed o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset float = floating, wpu = weak pull-up input port and control configuration t = true open drain, od = open drain, pp = push pull output bold x (pin state after internal reset release). reset state unless otherwise specified, the pin state is the same during the reset phase and after the internal reset release. 19/116 docid15590 rev 8 pinout and pin description stm8s903k3 stm8s903f3
stm8s903f3 tssop20/so20 pinout 5.1 figure 3: stm8s903f3 tssop20/so20 pinout 1. (hs) high sink capability. 2. (t) true open drain (p-buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). docid15590 rev 8 20/116 stm8s903k3 stm8s903f3 pinout and pin description 8 1 2 3 4 5 6 7 9 10 20 19 18 17 16 15 14 13 12 11 pd3(hs)/ain4/tim5_ch2/adc_etr tim5_ch1[u ar t1_ck]beep/pd4(hs) ain5/u ar t1_tx/pd5(hs) ain6/u ar t1_rx/pd6(hs) nrst oscin/p a1 oscout/p a2 v ss vcap v dd [spi_nss]/tim5_ch3/p a3(hs) pb4(t)/i2c_scl[adc_etr] pc3(hs)/tim1_ch3[tli][tim1_ch1n] pc4(hs)/tim1_ch4/clk_cco/ain2/[tim1_ch2n] pc5(hs)/spi_sck[tim5_ch1] pc6(hs)/spi_mosi[tim1_ch1] pc7(hs)/spi_miso[tim1_ch2] pd1(hs)/swim pd2(hs)/ain3[tim5_ch3] pb5(t)/[tim1_bkin]i2c_sd a
stm8s903f3 ufqfpn20 pinout 5.2 figure 4: stm8s903f3 ufqfpn20 pinout 1. (hs) high sink capability. 2. (t) true open drain (p-buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 21/116 docid15590 rev 8 pinout and pin description stm8s903k3 stm8s903f3 2 1 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 vcap v ss oscout/p a2 oscin/p a1 [u ar t1_tx]/ [spi_nss]/tim5_ch3/(hs) p a3 nrst pd4 (hs)/beep / tim5_ch1/u ar t1_ck pd5(hs)/ain5/u ar t1_tx pd3 (hs)/ain4/tim5_ch2/adc_etr pd2(hs)/ain3/[tim5_ch3] pc4(hs)/tim1_ch4/clk_cco/ain2/[tim1_ch2n] pc5 (hs)/spi_sck/[tim5_ch1] pc6(hs)/spi_mosi/[tim1_ch1] pc7(hs)/spi_miso/[tim1_ch2] pd1(hs)/swim [tim1_bkin]/i 2 c_sd a/(t)pb5 1 0 [tim1_ch1n]/[tli]/tim1_ch3/(hs)pc3 pd6(hs)/ain6/u ar t1_rx 20 v dd [adc_etr]/i 2 c_scl/(t)pb4
pin description tssop20_so20_ufqfpn20 5.3 table 5: tssop20/so20/ufqfpn20 pin description alternate function after remap [option bit] default alternate function main function (after reset) output input type pin name ufqfpn 20 tssop so20 ppod speed high sink (1) ext. interrupt wpu floating reset x i/o nrst 14 resonator/ crystal in port a1 xx o1 xx x i/o pa1/ oscin (2) 25 resonator/ crystal out port a2 xx o1 xx x i/o pa2/ oscout 36 digital ground s v ss 47 1.8 v regulator capacitor s vcap 58 digital power supply s v dd 69 spi master/ slave select [afr1]/ uart1 data transmit [afr1:0] timer 52 channel 3 port a3 xx o3 hs xx x i/o pa3/ tim5_ch3 [spi_nss] [uart1_tx] 710 timer 1 - break input [afr4] i 2 c data port b5 t (3) o1 x x i/o pb5/ i2c_sda [tim1_bkin] 811 adc external trigger [afr4] i 2 c clock port b4 t (3) o1 x x i/o pb4/ i2c_scl [adc_etr] 912 top level interrupt [afr3] timer 1 inverted channel 1 [afr7] timer 1 - channel 3 port c3 xx o3 hs xx x i/o pc3/ tim1_ch3/tli/[tim1_ch1n ] 10 13 analog input 2 [afr2]timer 1 inverted channel 2 [afr7] timer 1 - channel 4 /configurable clock output port c4 xx o3 hs xx x i/o pc4/ tim1_ch4/ clk_cco/ain2/[tim1_ch2n] 11 14 timer 5 channel 1 [afr0] spi clock port c5 xx o3 hs xx x i/o pc5/spi_sck [tim5_ch1] 12 15 timer 1 channel 1 [afr0] pi master out/slave in port c6 xx o3 hs xx x i/o pc6/ spi_mosi [tim1_ch1] 13 16 timer 1 channel 2[afr0] spi master in/ slave out port c7 xx o3 hs xx x i/o pc7/ spi_miso [tim1_ch2] 14 17 swim data interface port d1 xx o4 hs x x xi/o pd1/ swim (4) 15 18 analog input 3 [afr2] timer 52 - channel 3 [afr1] port d2 xx o3 hs xx x i/o pd2/ain3/ [tim5_ch3] 16 19 analog input 4 timer 52 - channel 2/adc external trigger port d3 xx o3 hs xx x i/o pd3/ ain4/ tim5_ch2/ adc_etr 17 20 uart clock [afr2] timer 5 - channel 1/beep output port d4 xx o3 hs xx x i/o pd4/ tim5_ch1/ beep [uart1_ck] 18 1 analog input 5/ uart1 data transmit port d5 xx o3 hs xx x i/o pd5/ ain5/ uart1_tx 19 2 analog input 6/ uart1 data receive port d6 xx o3 hs xx x i/o pd6/ ain6/ uart1_rx 20 3 (1) i/o pins used simultaneously for high current source/sink must be uniformly spaced around the package. in addition, the total driven current must respect the absolute maximum ratings ( see section "absolute maximum ratings"). (2) when the mcu is in halt/active-halt mode, pa1 is automatically configured in input weak pull-up and cannot be used for waking up the device. in this mode, the output state of pa1 is not driven. it is recommended to use pa1 only in input mode if halt/active-halt is used in the application. (3) in the open-drain output column, t defines a true open-drain i/o (p-buffer, weak pull-up, and protection diode to v dd are not implemented) (4) the pd1 pin is in input pull-up during the reset phase and after internal reset release. docid15590 rev 8 22/116 stm8s903k3 stm8s903f3 pinout and pin description
stm8s903k3 ufqfpn32/lqfp32/sdip32 pinout 5.4 figure 5: stm8s903k3 ufqfpn32/lqfp32 pinout 1. (hs) high sink capability. 2. (t) true open drain (p-buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). 23/116 docid15590 rev 8 pinout and pin description stm8s903k3 stm8s903f3 [adc_etr] i 2 c_scl/(t) pb4 tim1_etr/ain3/(hs) pb3 tim1_ch3n/ain2/ (hs) pb2 tim1_ch2n/ain1/(hs) pb1 tim1_ch1n/ain0/(hs) pb0 pb7 pb6 [tim1_bkin] i 2 c_sd a/(t) pb5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 vcap v dd [u ar t1_tx] [spi_nss] tim5_ch3/(hs) p a3 [u ar t1_rx] pf4 nrst oscin/p a1 oscout/p a2 v ss pc3 (hs) /tim1_ch3 [tli] [tim1_ch1n] pc2 (hs) /tim1_ch2 [tim1_ch3n] pc1 (hs) /tim1_ch1/ u ar t1_ck [tim1_ch2n] pe5/spi_nss [tim1_ch1n] pc7 (hs)/spi_miso [tim1_ch2] pc6 (hs)/spi_mosi [tim1_ch1] pc5 (hs)/spi_sck [tim5_ch1] pc4 (hs) /tim1_ch4/clk_cco [ain2] [tim1_ch2n] pd3 (hs)/ain4/tim5_ch2/adc_etr pd2 (hs)[ain3] [tim5_ch3] pd1 (hs)/swim pd0 (hs)/ tim1_bkin [clk_cco] pd7 (hs)/tli [ tim1_ch4] pd6 (hs)/ain6/u ar t1_rx pd5 (hs)/ain5/u ar t1_tx pd4 (hs)/beep/tim5_ch1 [ u ar t1_ck]
figure 6: stm8s903k3 sdip32 pinout 1. (hs) high sink capability. 2. (t) true open drain (p-buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). pin description 5.5 table 6: ufqfpn32/lqfp32/sdip32 pin description alternate function after remap [option bit] default alternate function main function (after reset) output input type pin name ufqfpn/ lqfp32 sdip 32 ppod speed high sink (1) ext. interrupt wpu floating reset x i/o nrst 16 resonator/ crystal in port a1 xx o1 xx x i/o pa1/ oscin (2) 27 resonator/ crystal out port a2 xx o1 xx x i/o pa2/ oscout 38 digital ground s v ss 49 1.8 v regulator capacitor s vcap 510 digital power supply s v dd 611 spi master/ slave select [afr1]/ uart1 data transmit [afr1:0] timer 52 channel 3 port a3 xx o3 hs xx x i/o pa3/ tim5_ch3 [spi_nss] [uart1_tx] 712 uart1 data receive [afr1:0] port f4 xx o1 x x i/o pf4 [uart1_rx] 813 port b7 xx o1 xx x i/o pb7 914 docid15590 rev 8 24/116 stm8s903k3 stm8s903f3 pinout and pin description 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ain4/tim5_ch2/adc_etr/pd3(hs) tim5_ch1[u ar t1_ck]beep/pd4(hs) ain5/u ar t1_tx/pd5(hs) ain6/u ar t1_rx/pd6(hs) [tim1_ch4]tli/pd7(hs) nrst oscin/p a1 oscout/p a2 v ss vcap v dd [u ar t1_tx][spi_nss]/tim5_ch3/p a3(hs) [u ar t1_rx]/pf4 pb6 pb4(t)/i2c_scl[adc_etr] pb3(hs)[ain3]tim1_etr pb2(hs)/ain2/tim1_ch3n pb1(hs)/ain1/tim1_ch2n pb0(hs)/ain0/tim1_ch1n pe5/spi_nss[tim1_ch1n] pc1(hs)/tim1_ch1/u ar t1_ck[tim1_ch2n] pc2(hs)/tim1_ch2[tim1_ch3n] pc3(hs)/tim1_ch3[tli][tim1_ch1n] pc4(hs)/tim1_ch4/clk_cco[ain2][tim1_ch2n] pc5(hs)/spi_sck[tim5_ch1] pc6(hs)/spi_mosi[tim1_ch1] pc7(hs)/spi_miso[tim1_ch2] pd0(hs)/tim1_bkin[clk_cco] pd1(hs)/swim pd2(hs)[ain3][tim5_ch3] pb7 [tim1_bkin]i2c_sd a/pb5(t)
alternate function after remap [option bit] default alternate function main function (after reset) output input type pin name ufqfpn/ lqfp32 sdip 32 ppod speed high sink (1) ext. interrupt wpu floating port b6 xx o1 xx x i/o pb6 10 15 timer 1 - break input [afr4] i 2 c data port b5 t (3) o1 x x i/o pb5/ i2c_sda [tim1_bkin] 1116 adc external trigger [afr4] i 2 c clock port b4 t (3) o1 x x i/o pb4/ i2c_scl [adc_etr] 12 17 analog input 3/ timer 1 external trigger port b3 xx o3 hs xx x i/o pb3/ ain3/tim1_etr 13 18 analog input 2/ timer 1 - inverted channel 3 port b2 xx o3 hs xx x i/o pb2/ ain2/ tim1_ch3n 14 19 analog input 1/ timer 1 - inverted channel 2 port b1 xx o3 hs xx x i/o pb1/ ain1/ tim1_ch2n 15 20 analog input 0/ timer 1 - inverted channel 1 port b0 xx o3 hs xx x i/o pb0/ ain0/ tim1_ch1n 16 21 timer 1 - inverted channel 1 [afr1:0] spi master/ slave select port e5 xx o3 hs xx x i/o pe5/ spi_nss [tim1_ch1n] 17 22 timer 1 - inverted channel 2 [afr1:0] timer 1 - channel 1 uart1 clock port c1 xx o3 hs xx x i/o pc1/ tim1_ch1/ uart1_ck [tim1_ch2n] 18 23 timer 1 - inverted channel 3 [afr1:0] timer 1 - channel 2 port c2 xx o3 hs xx x i/o pc2/ tim1_ch2 [tim1_ch3n] 19 24 top level interrupt [afr3] timer 1 inverted channel 1 [afr7] timer 1 - channel 3 port c3 xx o3 hs xx x i/o pc3/ tim1_ch3/tli/[tim1_ch1n ] 20 25 analog input 2 [afr2]timer 1 inverted channel 2 [afr7] timer 1 - channel 4 /configurable clock output port c4 xx o3 hs xx x i/o pc4/ tim1_ch4/ clk_cco/ain2/[tim1_ch2n] 21 26 timer 5 channel 1 [afr0] spi clock port c5 xx o3 hs xx x i/o pc5/spi_sck [tim5_ch1] 22 27 timer 1 channel 1 [afr0] pi master out/slave in port c6 xx o3 hs xx x i/o pc6/ spi_mosi [tim1_ch1] 23 28 timer 1 channel 2[afr0] spi master in/ slave out port c7 xx o3 hs xx x i/o pc7/ spi_miso [tim1_ch2] 24 29 configurable clock output [afr5] timer 1 - break input port d0 xx o3 hs xx x i/o pd0/ tim1_bkin [clk_cco] 25 30 swim data interface port d1 xx o4 hs x x xi/o pd1/ swim (4) 26 31 analog input 3 [afr2] timer 52 - channel 3 [afr1] port d2 xx o3 hs xx x i/o pd2/ain3/ [tim5_ch3] 27 32 analog input 4 timer 52 - channel 2/adc external trigger port d3 xx o3 hs xx x i/o pd3/ ain4/ tim5_ch2/ adc_etr 28 1 uart clock [afr2] timer 5 - channel 1/beep output port d4 xx o3 hs xx x i/o pd4/ tim5_ch1/ beep [uart1_ck] 29 2 analog input 5/ uart1 data transmit port d5 xx o3 hs xx x i/o pd5/ ain5/ uart1_tx 30 3 analog input 6/ uart1 data receive port d6 xx o3 hs xx x i/o pd6/ ain6/ uart1_rx 31 4 timer 1 - channel 4 [afr6] top level interrupt port d7 xx o3 hs xx x i/o pd7/ tli [tim1_ch4] 32 5 (1) i/o pins used simultaneously for high current source/sink must be uniformly spaced around the package. in addition, the total driven current must respect the absolute maximum ratings ( see section "absolute maximum ratings"). (2) when the mcu is in halt/active-halt mode, pa1 is automatically configured in input weak pull-up and cannot be used for waking up the device. in this mode, the output state of pa1 is not driven. it is recommended to use pa1 only in input mode if halt/active-halt is used in the application. (3) in the open-drain output column, t defines a true open-drain i/o (p-buffer, weak pull-up, and protection diode to v dd are not implemented) (4) the pd1 pin is in input pull-up during the reset phase and after internal reset release. 25/116 docid15590 rev 8 pinout and pin description stm8s903k3 stm8s903f3
alternate function remapping 5.6 as shown in the rightmost column of the pin description table, some alternate functions can be remapped at different i/o ports by programming one of eight afr (alternate function remap) option bits. when the remapping option is active, the default alternate function is no longer available. to use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. alternate function remapping does not effect gpio capabilities of the i/o ports (see the gpio section of the family reference manual, rm0016). docid15590 rev 8 26/116 stm8s903k3 stm8s903f3 pinout and pin description
memory and register map 6 memory map 6.1 figure 7: memory map 27/116 docid15590 rev 8 memory and register map stm8s903k3 stm8s903f3 0x00 9fff flash prog r am memor y (8 kb ytes) 0x00 0000 ram 0x00 03ff (1 kb yte) 513 b ytes stac k 0x00 4000 0x00 427f 640 b ytes data eepr om reser v ed reser v ed reser v ed 0x00 4280 0x00 a000 0x02 7fff 0x00 47ff 0x00 8000 32 interr upt v ectors 0x00 807f gpio and per iph. reg. 0x00 5000 0x00 57ff 0x00 5800 0x00 7fff 0x00 480b 0x00 4fff 0x00 7eff cpu/swim/deb ug/itc registers 0x00 7f00 reser v ed reser v ed option b ytes 0x00 480a 0x00 4800 0x00 0800 0x00 3fff 0x00 8080 reser v ed unique id 0x00 4864 0x00 4865 0x00 4870 0x00 4871
register map 6.2 i/o port hardware register map 6.2.1 table 7: i/o port hardware register map reset status register name register label block address 0x00 port a data output latch register pa_odr port a 0x00 5000 0xxx (1) port a input pin value register pa_idr 0x00 5001 0x00 port a data direction register pa_ddr 0x00 5002 0x00 port a control register 1 pa_cr1 0x00 5003 0x00 port a control register 2 pa_cr2 0x00 5004 0x00 port b data output latch register pb_odr port b 0x00 5005 0xxx (1) port b input pin value register pb_idr 0x00 5006 0x00 port b data direction register pb_ddr 0x00 5007 0x00 port b control register 1 pb_cr1 0x00 5008 0x00 port b control register 2 pb_cr2 0x00 5009 0x00 port c data output latch register pc_odr port c 0x00 500a 0xxx (1) port c input pin value register pb_idr 0x00 500b 0x00 port c data direction register pc_ddr 0x00 500c 0x00 port c control register 1 pc_cr1 0x00 500d 0x00 port c control register 2 pc_cr2 0x00 500e 0x00 port d data output latch register pd_odr port d 0x00 500f 0xxx (1) port d input pin value register pd_idr 0x00 5010 0x00 port d data direction register pd_ddr 0x00 5011 0x02 port d control register 1 pd_cr1 0x00 5012 0x00 port d control register 2 pd_cr2 0x00 5013 0x00 port e data output latch register pe_odr port e 0x00 5014 0xxx (1) port e input pin value register pe_idr 0x00 5015 0x00 port e data direction register pe_ddr 0x00 5016 0x00 port e control register 1 pe_cr1 0x00 5017 docid15590 rev 8 28/116 stm8s903k3 stm8s903f3 memory and register map
reset status register name register label block address 0x00 port e control register 2 pe_cr2 port e 0x00 5018 0x00 port f data output latch register pf_odr port f 0x00 5019 0xxx (1) port f input pin value register pf_idr 0x00 501a 0x00 port f data direction register pf_ddr 0x00 501b 0x00 port f control register 1 pf_cr1 0x00 501c 0x00 port f control register 2 pf_cr2 0x00 501d (1) depends on the external circuitry. general hardware register map 6.2.2 table 8: general hardware register map reset status register name register label block address reserved area (60 bytes) 0x00 501e to 0x00 5059 0x00 flash control register 1 flash_cr1 flash 0x00 505a 0x00 flash control register 2 flash_cr2 0x00 505b 0xff flash complementary control register 2 flash_ncr2 0x00 505c 0x00 flash protection register flash _fpr 0x00 505d 0xff flash complementary protection register flash _nfpr 0x00 505e 0x00 flash in-application programming status register flash _iapsr 0x00 505f reserved area (2 bytes) 0x00 5060 to 0x00 5061 0x00 flash program memory unprotection register flash _pukr flash 0x00 5062 reserved area (1 byte) 0x00 5063 29/116 docid15590 rev 8 memory and register map stm8s903k3 stm8s903f3
reset status register name register label block address 0x00 data eeprom unprotection register flash _dukr flash 0x00 5064 reserved area (59 bytes) 0x00 5065 to 0x00 509f 0x00 external interrupt control register 1 exti_cr1 itc 0x00 50a0 0x00 external interrupt control register 2 exti_cr2 0x00 50a1 reserved area (17 bytes) 0x00 50a2 to 0x00 50b2 0xxx (1) reset status register rst_sr rst 0x00 50b3 reserved area (12 bytes) 0x00 50b4 to 0x00 50bf 0x01 internal clock control register clk_ickr clk 0x00 50c0 0x00 external clock control register clk_eckr 0x00 50c1 reserved area (1 byte) 0x00 50c2 0xe1 clock master status register clk_cmsr clk 0x00 50c3 0xe1 clock master switch register clk_swr 0x00 50c4 0xxx clock switch control register clk_swcr 0x00 50c5 0x18 clock divider register clk_ckdivr 0x00 50c6 0xff peripheral clock gating register 1 clk_pckenr1 0x00 50c7 0x00 clock security system register clk_cssr 0x00 50c8 0x00 configurable clock control register clk_ccor 0x00 50c9 0xff peripheral clock gating register 2 clk_pckenr2 0x00 50ca docid15590 rev 8 30/116 stm8s903k3 stm8s903f3 memory and register map
reset status register name register label block address 0x00 hsi clock calibration trimming register clk_hsitrimr 0x00 50cc 0bxxxx xxx0 swim clock control register clk_swimccr 0x00 50cd reserved area (3 bytes) 0x00 50ce to 0x00 50d0 0x7f wwdg control register wwdg_cr wwdg 0x00 50d1 0x7f wwdr window register wwdg_wr 0x00 50d2 reserved area (13 bytes) 0x00 50d3 to 00 50df 0xxx (2) iwdg key register iwdg_kr iwdg 0x00 50e0 0x00 iwdg prescaler register iwdg_pr 0x00 50e1 0xff iwdg reload register iwdg_rlr 0x00 50e2 reserved area (13 bytes) 0x00 50e3 to 0x00 50ef 0x00 awu control/status register 1 awu_csr1 awu 0x00 50f0 0x3f awu asynchronous prescaler buffer register awu_apr 0x00 50f1 0x00 awu timebase selection register awu_tbr 0x00 50f2 0x1f beep control/status register beep_csr beep 0x00 50f3 reserved area (12 bytes) 0x00 50f4 to 0x00 50ff 0x00 spi control register 1 spi_cr1 spi 0x00 5200 0x00 spi control register 2 spi_cr2 0x00 5201 31/116 docid15590 rev 8 memory and register map stm8s903k3 stm8s903f3
reset status register name register label block address 0x00 spi interrupt control register spi_icr 0x00 5202 0x02 spi status register spi_sr 0x00 5203 0x00 spi data register spi_dr 0x00 5204 0x07 spi crc polynomial register spi_crcpr 0x00 5205 0xff spi rx crc register spi_rxcrcr 0x00 5206 0xff spi tx crc register spi_txcrcr 0x00 5207 reserved area (8 bytes) 0x00 5208 to 0x00 520f 0x00 i 2 c control register 1 i2c_cr1 i 2 c 0x00 5210 0x00 i 2 c control register 2 i2c_cr2 0x00 5211 0x00 i 2 c frequency register i2c_freqr 0x00 5212 0x00 i 2 c own address register low i2c_oarl 0x00 5213 0x00 i 2 c own address register high i2c_oarh 0x00 5214 reserved 0x00 5215 0x00 i 2 c data register i2c_dr 0x00 5216 0x00 i 2 c status register 1 i2c_sr1 0x00 5217 0x00 i 2 c status register 2 i2c_sr2 0x00 5218 0x0x i 2 c status register 3 i2c_sr3 0x00 5219 0x00 i 2 c interrupt control register i2c_itr 0x00 521a 0x00 i 2 c clock control register low i2c_ccrl 0x00 521b docid15590 rev 8 32/116 stm8s903k3 stm8s903f3 memory and register map
reset status register name register label block address 0x00 i 2 c clock control register high i2c_ccrh 0x00 521c 0x02 i 2 c trise register i2c_triser 0x00 521d 0x00 i 2 c packet error checking register i2c_pecr 0x00 521e reserved area (17 bytes) 0x00 521f to 0x00 522f 0xc0 uart1 status register uart1_sr uart1 0x00 5230 0xxx uart1 data register uart1_dr 0x00 5231 0x00 uart1 baud rate register 1 uart1_brr1 0x00 5232 0x00 uart1 baud rate register 2 uart1_brr2 0x00 5233 0x00 uart1 control register 1 uart1_cr1 0x00 5234 0x00 uart1 control register 2 uart1_cr2 0x00 5235 0x00 uart1 control register 3 uart1_cr3 0x00 5236 0x00 uart1 control register 4 uart1_cr4 0x00 5237 0x00 uart1 control register 5 uart1_cr5 0x00 5238 0x00 uart1 guard time register uart1_gtr 0x00 5239 0x00 uart1 precaler register uart1_pscr 0x00 523a reserved area (21 bytes) 0x00 523b to 0x00 523f 0x00 tim1 control register 1 tim1_cr1 tim1 0x00 5250 0x00 tim1 control register 2 tim1_cr2 0x00 5251 33/116 docid15590 rev 8 memory and register map stm8s903k3 stm8s903f3
reset status register name register label block address 0x00 tim1 slave mode control register tim1_smcr 0x00 5252 0x00 tim1 external trigger register tim1_etr 0x00 5253 0x00 tim1 interrupt enable register tim1_ier 0x00 5254 0x00 tim1 status register 1 tim1_sr1 0x00 5255 0x00 tim1 status register 2 tim1_sr2 0x00 5256 0x00 tim1 event generation register tim1_egr 0x00 5257 0x00 tim1 capture/compare mode register 1 tim1_ccmr1 0x00 5258 0x00 tim1 capture/compare mode register 2 tim1_ccmr2 0x00 5259 0x00 tim1 capture/compare mode register 3 tim1_ccmr3 0x00 525a 0x00 tim1 capture/compare mode register 4 tim1_ccmr4 0x00 525b 0x00 tim1 capture/compare enable register 1 tim1_ccer1 0x00 525c 0x00 tim1 capture/compare enable register 2 tim1_ccer2 0x00 525d 0x00 tim1 counter high tim1_cntrh 0x00 525e 0x00 tim1 counter low tim1_cntrl 0x00 525f 0x00 tim1 prescaler register high tim1_pscrh 0x00 5260 0x00 tim1 prescaler register low tim1_pscrl 0x00 5261 0xff tim1 auto-reload register high tim1_arrh 0x00 5262 0xff tim1 auto-reload register low tim1_arrl 0x00 5263 0x00 tim1 repetition counter register tim1_rcr 0x00 5264 0x00 tim1 capture/compare register 1 high tim1_ccr1h 0x00 5265 docid15590 rev 8 34/116 stm8s903k3 stm8s903f3 memory and register map
reset status register name register label block address 0x00 tim1 capture/compare register 1 low tim1_ccr1l 0x00 5266 0x00 tim1 capture/compare register 2 high tim1_ccr2h 0x00 5267 0x00 tim1 capture/compare register 2 low tim1_ccr2l 0x00 5268 0x00 tim1 capture/compare register 3 high tim1_ccr3h 0x00 5269 0x00 tim1 capture/compare register 3 low tim1_ccr3l 0x00 526a 0x00 tim1 capture/compare register 4 high tim1_ccr4h 0x00 526b 0x00 tim1 capture/compare register 4 low tim1_ccr4l 0x00 526c 0x00 tim1 break register tim1_bkr 0x00 526d 0x00 tim1 dead-time register tim1_dtr 0x00 526e 0x00 tim1 output idle state register tim1_oisr 0x00 526f reserved area (147 bytes) 0x00 5270 to 0x00 52ff 0x00 tim5 control register 1 tim5_cr1 tim5 0x00 5300 0x00 tim5 control register 2 tim5_cr2 0x00 5301 0x00 tim5 slave mode control register tim5_smcr 0x00 5302 0x00 tim5 interrupt enable register tim5_ier 0x00 5303 0x00 tim5 status register 1 tim5_sr1 0x00 5304 0x00 tim5 status register 2 tim5_sr2 0x00 5305 0x00 tim5 event generation register tim5_egr 0x00 5306 0x00 tim5 capture/compare mode register 1 tim5_ccmr1 0x00 5307 35/116 docid15590 rev 8 memory and register map stm8s903k3 stm8s903f3
reset status register name register label block address 0x00 tim5 capture/compare mode register 2 tim5_ccmr2 0x00 5308 0x00 tim5 capture/compare mode register 3 tim5_ccmr3 0x00 5309 0x00 tim5 capture/compare enable register 1 tim5_ccer1 0x00 530a 0x00 tim5 capture/compare enable register 2 tim5_ccer2 0x00 530b 0x00 tim5 counter high tim5_cntrh 00 530c0x 0x00 tim5 counter low tim5_cntrl 0x00 530d 0x00 tim5 prescaler register tim5_pscr 0x00 530e 0xff tim5 auto-reload register high tim5_arrh 0x00 530f 0xff tim5 auto-reload register low tim5_arrl 0x00 5310 0x00 tim5 capture/compare register 1 high tim5_ccr1h 0x00 5311 0x00 tim5 capture/compare register 1 low tim5_ccr1l 0x00 5312 0x00 tim5 capture/compare register 2 high tim5_ccr2h 0x00 5313 0x00 tim5 capture/compare register 2 low tim5_ccr2l 0x00 5314 0x00 tim5 capture/compare register 3 high tim5_ccr3h 0x00 5315 0x00 tim5 capture/compare register 3 low tim5_ccr3l 0x00 5316 reserved area (43 bytes) 0x00 5317 to 0x00 533f 0x00 tim6 control register 1 tim6_cr1 tim6 0x00 5340 0x00 tim6 control register 2 tim6_cr2 0x00 5341 0x00 tim6 slave mode control register tim6_smcr 0x00 5342 docid15590 rev 8 36/116 stm8s903k3 stm8s903f3 memory and register map
reset status register name register label block address 0x00 tim6 interrupt enable register tim6_ier 0x00 5343 0x00 tim6 status register tim6_sr 0x00 5344 0x00 tim6 event generation register tim6_egr 0x00 5345 0x00 tim6 counter tim6_cntr 0x00 5346 0x00 tim6 prescaler register tim6_pscr 0x00 5347 0xff tim6 auto-reload register tim6_arr 0x00 5348 reserved area (153 bytes) 0x00 5349 to 0x00 53df 0x00 adc data buffer registers adc _dbxr adc1 0x00 53e0 to 0x00 53f3 reserved area (12 bytes) 0x00 53f4 to 0x00 53ff 0x00 adc control/status register adc _csr adc1 contd 0x00 5400 0x00 adc configuration register 1 adc_cr1 0x00 5401 0x00 adc configuration register 2 adc_cr2 0x00 5402 0x00 adc configuration register 3 adc_cr3 0x00 5403 0xxx adc data register high adc_drh 0x00 5404 0xxx adc data register low adc_drl 0x00 5405 0x00 adc schmitt trigger disable register high adc_tdrh 0x00 5406 0x00 adc schmitt trigger disable register low adc_tdrl 0x00 5407 0x03 adc high threshold register high adc_htrh 0x00 5408 37/116 docid15590 rev 8 memory and register map stm8s903k3 stm8s903f3
reset status register name register label block address 0xff adc high threshold register low adc_htrl 0x00 5409 0x00 adc low threshold register high adc_ltrh 0x00 540a 0x00 adc low threshold register low adc_ltrl 0x00 540b 0x00 adc analog watchdog status register high adc_awsrh 0x00 540c 0x00 adc analog watchdog status register low adc_awsrl 0x00 540d 0x00 adc analog watchdog control register high adc _awcrh 0x00 540e 0x00 adc analog watchdog control register low adc_awcrl 0x00 540f reserved area (1008 bytes) 0x00 5410 to 0x00 57ff (1) depends on the previous reset source. (2) write only register. cpu/swim/debug module/interrupt controller registers 6.2.3 table 9: cpu/swim/debug module/interrupt controller registers reset status register name register label block address 0x00 accumulator a cpu (1) 0x00 7f00 0x00 program counter extended pce 0x00 7f01 0x00 program counter high pch 0x00 7f02 0x00 program counter low pcl 0x00 7f03 0x00 x index register high xh 0x00 7f04 0x00 x index register low xl 0x00 7f05 0x00 y index register high yh 0x00 7f06 0x00 y index register low yl 0x00 7f07 0x03 stack pointer high sph 0x00 7f08 docid15590 rev 8 38/116 stm8s903k3 stm8s903f3 memory and register map
reset status register name register label block address 0xff stack pointer low spl 0x00 7f09 0x28 condition code register ccr 0x00 7f0a reserved area (85 bytes) 0x00 7f0b to 0x00 7f5f 0x00 global configuration register cfg_gcr cpu 0x00 7f60 0xff interrupt software priority register 1 itc_spr1 itc 0x00 7f70 0xff interrupt software priority register 2 itc_spr2 0x00 7f71 0xff interrupt software priority register 3 itc_spr3 0x00 7f72 0xff interrupt software priority register 4 itc_spr4 0x00 7f73 0xff interrupt software priority register 5 itc_spr5 0x00 7f74 0xff interrupt software priority register 6 itc_spr6 0x00 7f75 0xff interrupt software priority register 7 itc_spr7 0x00 7f76 0xff interrupt software priority register 8 itc_spr8 0x00 7f77 reserved area (2 bytes) 0x00 7f78 to 0x00 7f79 0x00 swim control status register swim_csr swim 0x00 7f80 reserved area (15 bytes) 0x00 7f81 to 0x00 7f8f 0xff dm breakpoint 1 register extended byte dm_bk1re dm 0x00 7f90 0xff dm breakpoint 1 register high byte dm_bk1rh 0x00 7f91 0xff dm breakpoint 1 register low byte dm_bk1rl 0x00 7f92 0xff dm breakpoint 2 register extended byte dm_bk2re 0x00 7f93 0xff dm breakpoint 2 register high byte dm_bk2rh 0x00 7f94 0xff dm breakpoint 2 register low byte dm_bk2rl 0x00 7f95 0x00 dm debug module control register 1 dm_cr1 0x00 7f96 0x00 dm debug module control register 2 dm_cr2 0x00 7f97 0x10 dm debug module control/status register 1 dm_csr1 0x00 7f98 0x00 dm debug module control/status register 2 dm_csr2 0x00 7f99 39/116 docid15590 rev 8 memory and register map stm8s903k3 stm8s903f3
reset status register name register label block address 0xff dm enable function register dm_enfctr 0x00 7f9a reserved area (5 bytes) 0x00 7f9b to 0x00 7f9f (1) accessible by debug module only docid15590 rev 8 40/116 stm8s903k3 stm8s903f3 memory and register map
interrupt vector mapping 7 table 10: interrupt mapping vector address wakeup from active-halt mode wakeup from halt mode description source block irq no. 0x00 8000 yes yes reset reset 0x00 8004 - - software interrupt trap 0x00 8008 - - external top level interrupt tli0 0x00 800c yes - auto wake up from halt awu1 0x00 8010 - - clock controller clk2 0x00 8014 yes (1) yes (1) port a external interrupts exti0 3 0x00 8018 yes yes port b external interrupts exti1 4 0x00 801c yes yes port c external interrupts exti2 5 0x00 8020 yes yes port d external interrupts exti3 6 0x00 8024 yes yes port e external interrupts exti4 7 0x00 8028 port f exti5 8 0x00 802c - - reserved 9 0x00 8030 yes yes end of transfer spi10 0x00 8034 - - tim1 update/ overflow/ underflow/ trigger/ break tim111 0x00 8038 - - tim1 capture/ compare tim112 0x00 803c - - tim5 update/ overflow/ trigger tim513 0x00 8040 - - tim5 capture/ compare tim514 0x00 8044 - - reserved 15 0x00 8048 - - reserved 16 0x00 804c - - tx complete uart1 17 0x00 8050 - - receive register data full uart1 18 0x00 8054 yes yes i 2 c interrupt i 2 c19 0x00 8058 - - reserved 20 0x00 805c - - reserved 21 41/116 docid15590 rev 8 interrupt vector mapping stm8s903k3 stm8s903f3
vector address wakeup from active-halt mode wakeup from halt mode description source block irq no. 0x00 8060 - - adc1 end of conversion/ analog watchdog interrupt adc1 22 0x00 8064 - - tim6 update/ overflow/ trigger tim623 0x00 8068 - - eop/ wr_pg_dis flash24 0x00 806c to 0x00 807c reserved (1) except pa1 docid15590 rev 8 42/116 stm8s903k3 stm8s903f3 interrupt vector mapping
option bytes 8 option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory. except for the rop (read-out protection) byte, each option byte has to be stored twice, in a regular form (optx) and a complemented one (noptx) for redundancy. option bytes can be modified in icp mode (via swim) by accessing the eeprom address shown in the table below. option bytes can also be modified on the fly by the application in iap mode, except the rop option that can only be modified in icp mode (via swim). refer to the stm8s flash programming manual (pm0051) and stm8 swim communication protocol and debug module user manual (um0470) for information on swim programming procedures. table 11: option bytes factory default setting option bits option byte no. option name addr. 0 12 3 4 56 7 0x00 rop [7:0] opt0 read-out protection (rop) 0x4800 0x00 ubc [7:0] opt1 user boot code(ubc) 0x4801 0xff nubc [7:0] nopt1 0x4802 0x00 afr0 afr1 afr2 afr3 afr4 afr5 afr6 afr7 opt2 alternate function 0x4803 0xff nafr0 nafr1 nafr2 nafr3 nafr4 nafr5 nafr6 nafr7 nopt2 0x4804 remapping (afr) 0x00 wwdg _halt wwdg _hw iwdg _hw lsi_ en hsi trim reserved opt3 miscell. option 0x4805h 0xff nww g_halt nwwdg _hw niwdg _hw nlsi_ en nhsi trim reserved nopt3 0x4806 0x00 prs c0 prs c1 ckawu sel ext clk reserved opt4 clock option 0x4807 0xff npr sc0 nprsc1 ncka wusel next clk reserved nopt4 0x4808 0x00 hsecnt [7:0] opt5 hse clock startup 0x4809 0xff nhsecnt [7:0] nopt5 0x480a table 12: option byte description description option byte no. rop[7:0] memory readout protection (rop) opt0 0xaa: enable readout protection (write access via swim protocol) 43/116 docid15590 rev 8 option bytes stm8s903k3 stm8s903f3
description option byte no. note: refer to the family reference manual (rm0016) section on flash/eeprom memory readout protection for details. ubc[7:0] user boot code area opt1 0x00: no ubc, no write-protection 0x01: page 0 defined as ubc, memory write-protected 0x02: pages 0 to 1 defined as ubc, memory write-protected. page 0 and 1 contain the interrupt vectors. ... 0x7f: pages 0 to 126 defined as ubc, memory write-protected other values: pages 0 to 127 defined as ubc, memory write-protected note: refer to the family reference manual (rm0016) section on flash write protection for more details. afr[7:0] opt2 refer to following section for alternate function remapping decriptions of bits [7:2] and [1:0] respectively. hsitrim :high speed internal clock trimming register size opt3 0: 3-bit trimming supported in clk_hsitrimr register 1: 4-bit trimming supported in clk_hsitrimr register lsi_en :low speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw : independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchdog activated by hardware wwdg_hw : window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_halt : window watchdog reset on halt docid15590 rev 8 44/116 stm8s903k3 stm8s903f3 option bytes
description option byte no. 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active extclk : external clock selection opt4 0: external crystal connected to oscin/oscout 1: external clock signal on oscin ckawusel :auto wake-up unit/clock 0: lsi clock source selected for awu 1: hse clock with prescaler selected as clock source for for awu prsc[1:0] awu clock prescaler 0x: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 11: 4 mhz to 128 khz prescaler hsecnt[7:0] :hse crystal oscillator stabilization time opt5 0x00: 2048 hse cycles 0xb4: 128 hse cycles 0xd2: 8 hse cycles 0xe1: 0.5 hse cycles stm8s903k3/f3 alternate function remapping bits 8.1 table 13: stm8s903k3 alternate function remapping bits [7:2] for 32-pin packages description (1) option byte no. afr7 alternate function remapping option 7 opt2 0: afr7 remapping option inactive: default alternate functions (2) . 1: port c3 alternate function = tim1_ch1n; port c4 alternate function = tim1_ch2n. afr6 alternate function remapping option 6 0: afr6 remapping option inactive: default alternate function (2) . 1: port d7 alternate function = tim1_ch4. 45/116 docid15590 rev 8 option bytes stm8s903k3 stm8s903f3
description (1) option byte no. afr5 alternate function remapping option 5 0: afr5 remapping option inactive: default alternate function (2) . 1: port d0 alternate function = clk_cco. afr4 alternate function remapping option 4 0: afr4 remapping option inactive: default alternate functions (2) . 1: port b4 alternate function = adc_etr; port b5 alternate function = tim1_bkin. afr3 alternate function remapping option 3 0: afr3 remapping option inactive: default alternate function (2) . 1: port c3 alternate function = tli. afr2 alternate function remapping option 2 0: afr2 remapping option inactive: default alternate functions (2) . 1: port c4 alternate function = ain2; port d2 alternate function = ain3; port d4 alternate function = uart1_ck. (1) do not use more than one remapping option in the same port. (2) refer to pinout description. table 14: stm8s903f3 alternate function remapping bits [7:2] for 20-pin packages description (1) option byte no. afr7 alternate function remapping option 7 opt2 0: afr7 remapping option inactive: default alternate functions (2) 1: port c3 alternate function = tim1_ch1n; port c4 alternate function = tim1_ch2n. afr6 alternate function remapping option 6 reserved. afr5 alternate function remapping option 5 reserved. afr4 alternate function remapping option 4 0: afr4 remapping option inactive: default alternate functions (2) . 1: port b4 alternate function = adc_etr; port b5 alternate function = tim1_bkin. afr3 alternate function remapping option 3 docid15590 rev 8 46/116 stm8s903k3 stm8s903f3 option bytes
description (1) option byte no. 0: afr3 remapping option inactive: default alternate function (2) . 1: port c3 alternate function = tli. afr2 alternate function remapping option 2 reserved. (1) do not use more than one remapping option in the same port. (2) refer to pinout description. table 15: stm8s903k3 alternate function remapping bits [1:0] for 32-pin packages alternate function mapping i/o port afr0 option bit value afr1 option bit value afr1 and afr0 remapping options inactive: default alternate functions (1) 0 0 tim5_ch1 pc5 1 0 tim1_ch1 pc6 tim1_ch2 pc7 spi_nss pa3 0 1 tim5_ch3 pd2 tim5_ch3 pd2 1 1 tim5_ch1 pc5 tim1_ch1 pc6 tim1_ch2 pc7 tim1_ch3n pc2 tim1_ch2n pc1 tim1_ch1n pe5 uart1_tx pa3 uart1_rx pf4 (1) refer to pinout description. 47/116 docid15590 rev 8 option bytes stm8s903k3 stm8s903f3
table 16: stm8s903f3 alternate function remapping bits [1:0] for 20-pin packages alternate function mapping i/o port afr0 option bit value afr1 option bit value afr1 and afr0 remapping options inactive: default alternate functions (1) 0 0 tim5_ch1 pc5 1 0 tim1_ch1 pc6 tim1_ch2 pc7 spi_nss pa3 0 1 tim5_ch3 pd2 tim5_ch3 pd2 1 1 tim5_ch1 pc5 tim1_ch1 pc6 tim1_ch2 pc7 pc2 pc1 tim1_ch1n pe5 uart1_tx pa3 uart1_rx pf4 (1) refer to pinout description. docid15590 rev 8 48/116 stm8s903k3 stm8s903f3 option bytes
unique id 9 the devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. the 96 bits of the identifier can never be altered by the user. the unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. the unique device identifier is ideally suited: ? for use as serial numbers ? for use as security keys to increase the code security in the program memory while using and combining this unique id with software cryptograhic primitives and protocols before programming the internal memory. ? to activate secure boot processes table 17: unique id registers (96 bits) unique id bits content description address 01234567 u_id[7:0] x co-ordinate on the wafer 0x4865 u_id[15:8] 0x4866 u_id[23:16] y co-ordinate on the wafer 0x4867 u_id[31:24] 0x4868 u_id[39:32] wafer number 0x4869 u_id[47:40] lot number 0x486a u_id[55:48] 0x486b u_id[63:56] 0x486c u_id[71:64] 0x486d u_id[79:72] 0x486e u_id[87:80] 0x486f u_id[95:88] 0x4870 49/116 docid15590 rev 8 unique id stm8s903k3 stm8s903f3
electrical characteristics 10 parameter conditions 10.1 unless otherwise specified, all voltages are referred to v ss . minimum and maximum values 10.1.1 unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at t a = 25 c and t a = t amax (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). typical values 10.1.2 unless otherwise specified, typical data are based on t a = 25 c, v dd = 5 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ). typical curves 10.1.3 unless otherwise specified, all typical curves are given only as design guidelines and are not tested. loading capacitor 10.1.4 the loading conditions used for pin parameter measurement are shown in the following figure. figure 8: pin loading conditions pin input voltage 10.1.5 the input voltage measurement on a pin of the device is described in the following figure. docid15590 rev 8 50/116 stm8s903k3 stm8s903f3 electrical characteristics 5 0 p f stm 8 p i n
figure 9: pin input voltage absolute maximum ratings 10.2 stresses above those listed as absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 18: voltage characteristics unit max min ratings symbol v 6.5 -0.3 supply voltage (1) v ddx - v ss 6.5 v ss - 0.3 input voltage on true open drain pins (2) v in v dd + 0.3 v ss - 0.3 input voltage on any other pin (2) mv 50 - variations between different power pins |v ddx - v dd | 50 - variations between all the different ground pins |v ssx - v ss | see "absolute maximum ratings (electrical sensitivity)" electrostatic discharge voltage v esd (1) all power (v dd ) and ground (v ss ) pins must always be connected to the external power supply (2) i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in unit max (1) ratings symbol 80 total current out of v ss ground lines (sink) (2) i vss 20 output current sunk by any i/o and control pin i io - 20 output current source by any i/os and control pin 4 injected current on nrst pin i inj(pin) (3) (4) 4 injected current on oscin pin 4 injected current on any other pin (5) 20 total injected current (sum of all i/o and control pins) (5) i inj(pin) (3) (1) data based on characterization results, not tested in production. (2) all power (v dd ) and ground (v ss ) pins must always be connected to the external supply. (3) i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in operating conditions 10.3 table 21: general operating conditions unit max min conditions parameter symbol mhz 160 internal cpu clock frequency f cpu v 5.5 2.95 standard operating voltage v dd nf 3300 470 c ext : capacitance of external capacitor vcap (1) 0.3- at 1 mhz (2) esr of external capacitor nh 15- esl of external capacitor mw 182- tssop20 power dissipation at t a = 85 c for suffix 6 p d (3) 1000 - so20w 198- ufqfpn20 333- lqfp32 526- ufqfpn32 333- sdip32 45- tssop20 power dissipation at t a = 125 c for suffix 3 250- so20w 49- ufqfpn20 83- lqfp32 132- ufqfpn32 83- sdip32 c 85 -40 maximum power dissipation ambient temperature for 6 suffix version t a 125 -40 maximum power dissipation ambient temperature for 3 suffix version 105 -40 6 suffix version junction temperature range t j 130 -40 3 suffix version (1) care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, dc bias and frequency in addition to other factors. the parameter maximum value must be respected for the full application range. (2) this frequency of 1 mhz as a condition for vcap parameters is given by design of internal regulator 53/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
(3) to calculate p dmax (t a ), use the formula p dmax = (t jmax - t a )/ ja (see thermal characteristics ). figure 10: f cpumax versus v dd table 22: operating conditions at power-up/power-down unit max typ min conditions parameter symbol s/v 2 v dd rise time rate t vdd 2 v dd fall time rate (1) ms1.7 v dd rising reset release delay t temp v2.85 2.7 2.6 power-on reset threshold v it+ 2.8 2.65 2.5 brown-out reset threshold v it- mv 70 brown-out reset hysteresis v hys(bor) (1) reset is always generated after a t temp delay. the application must ensure that v dd is still above the minimum ooperating voltage (v dd min) when the t temp delay has elapsed. vcap external capacitor 10.3.1 stabilization for the main regulator is achieved connecting an external capacitor c ext to the v cap pin. c ext is specified in the operating conditions section. care should be taken to limit the series inductance to less than 15 nh. docid15590 rev 8 54/116 stm8s903k3 stm8s903f3 electrical characteristics 16 12 8 4 0 2.95 4.0 5.0 5.5 f cpu (mhz) functionality guar anteed @t a -40 to 125 c supply v oltage functionality not guar anteed in this area
figure 11: external capacitor c ext 1. esr is the equivalent series resistance and esl is the equivalent inductance. supply current characteristics 10.3.2 the current consumption is measured as described in pin input voltage . total current consumption in run mode 10.3.2.1 the mcu is placed under the following conditions: ? all i/o pins in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled (clock stopped by peripheral clock gating registers) except if explicitly mentioned. subject to general operating conditions for v dd and t a . table 23: total current consumption with code execution in run mode at v dd = 5 v unit max (1) typ conditions parameter symbol ma -2.3 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in run mode, code executed from ram i dd(run) 2.352 hse user ext. clock (16 mhz) 21.7 hsi rc osc. (16 mhz) -0.86 hse user ext. clock (16 mhz) f cpu = f master /128 = 125 khz 0.87 0.7 hsi rc osc. (16 mhz) 0.58 0.46 hsi rc osc. (16 mhz/8) f cpu = f master /128 = 15.625 khz 0.55 0.41 lsi rc osc. (128 khz) f cpu = f master = 128 khz -4.5 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in run mode, code executed from flash 4.75 4.3 hse user ext. clock (16 mhz) 4.5 3.7 hsi rc osc. (16 mhz) ma 1.05 0.84 hsi rc osc. (16 mhz/8) (2) f cpu = f master = 2 mhz supply current in run mode, code executed from flash i dd(run) 55/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3 c rlea k es r e s l
unit max (1) typ conditions parameter symbol 0.9 0.72 hsi rc osc. (16 mhz) f cpu = f master /128 = 125 khz 0.58 0.46 hsi rc osc. (16 mhz/8) f cpu = f master /128 = 15.625 khz 0.57 0.42 lsi rc osc. (128 khz) f cpu = f master = 128 khz (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals off. table 24: total current consumption with code execution in run mode at v dd = 3.3 v unit max (1) typ conditions parameter symbol ma -1.8 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in run mode, code executed from ram i dd(run) 2.32 hse user ext. clock (16 mhz) 21.5 hsi rc osc. (16 mhz) -0.81 hse user ext. clock (16 mhz) f cpu = f master / 128 = 125 khz 0.87 0.7 hsi rc osc. (16 mhz) 0.58 0.46 hsi rc osc. (16 mhz/8) f cpu = f master / 128 = 15.625 khz 0.55 0.41 lsi rc osc. (128 khz) f cpu = f master = 128 khz -4 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in run mode, code executed from flash 4.73.9 hse user ext. clock (16 mhz) 4.53.7 hsi rc osc. (16 mhz) 1.05 0.84 hsi rc osc. (16 mhz/8) (2) f cpu = f master = 2 mhz 0.9 0.72 hsi rc osc. (16 mhz) f cpu = f master / 128 = 125 khz 0.58 0.46 hsi rc osc. (16 mhz/8) f cpu = f master / docid15590 rev 8 56/116 stm8s903k3 stm8s903f3 electrical characteristics
unit max (1) typ conditions parameter symbol 128 = 15.625 khz 0.57 0.42 lsi rc osc. (128 khz) f cpu = f master = 128 khz (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals off. total current consumption in wait mode 10.3.2.2 table 25: total current consumption in wait mode at v dd = 5 v unit max (1) typ conditions parameter symbol ma -1.6 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in wait mode i dd(wfi) 1.31.1 hse user ext. clock (16 mhz) 1.1 0.89 hsi rc osc. (16 mhz) 0.88 0.7 hsi rc osc. (16 mhz) f cpu = f master /128 = 125 khz 0.57 0.45 hsi rc osc. (16 mhz/8) (2) f cpu = f master /128 = 15.625 khz 0.54 0.4 lsi rc osc. (128 khz) f cpu = f master = 128 khz (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals off. table 26: total current consumption in wait mode at v dd = 3.3 v unit max (1) typ conditions parameter symbol ma - 1.1 hse crystal osc. (16 mhz) f cpu = f master = 16 mhz supply current in wait mode i dd(wfi) 1.3 1.1 hse user ext. clock (16 mhz) 57/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
unit max (1) typ conditions parameter symbol 1.1 0.89 hsi rc osc. (16 mhz) 0.88 0.7 hsi rc osc. (16 mhz) f cpu = f master / 128 = 125 khz 0.57 0.45 hsi rc osc. (16 mhz/8) (2) f cpu = f master / 128 = 15.625 khz 0.54 0.4 lsi rc osc. (128 khz) f cpu = f master = 128 khz (1) data based on characterization results, not tested in production. (2) default clock configuration measured with all peripherals off. total current consumption in active halt mode 10.3.2.3 table 27: total current consumption in active halt mode at v dd = 5 v unit max at 125 c (1) max at 85 c (1) typ conditions parameter symbol clock source flash mode (3) main voltage regulator (mvr) (2) a --1030 hse crystal osc. (16 mhz) operating mode on supply current in active halt mode i dd(ah) 300260200 lsi rc osc. (128 khz) operating mode on supply current in active halt mode i dd(ah) --970 hse crystal osc. (16 mhz) power-down mode on supply current in active halt mode i dd(ah) 230200150 lsi rc osc. (128 khz) power-down mode on supply current in active halt mode i dd(ah) 1108566 lsi rc osc. (128 khz) operating mode off supply current in active halt mode i dd(ah) docid15590 rev 8 58/116 stm8s903k3 stm8s903f3 electrical characteristics
unit max at 125 c (1) max at 85 c (1) typ conditions parameter symbol clock source flash mode (3) main voltage regulator (mvr) (2) 402010 lsi rc osc. (128 khz) power-down mode supply current in active halt mode i dd(ah) (1) data based on characterization results, not tested in production (2) configured by the regah bit in the clk_ickr register. (3) configured by the ahalt bit in the flash_cr1 register. table 28: total current consumption in active halt mode at v dd = 3.3 v unit max at 125 c (1) max at 85 c (1) typ conditions parameter symbol clock source flash mode (3) main voltage regulator (mvr) (2) a--550 hse crystal osc. (16 mhz) operating mode on supply current in active halt mode i dd(ah) a 290 260 200 lsi rc osc. (128 khz) operating mode on supply current in active halt mode i dd(ah) --970 hse crystal osc. (16 mhz) power-down mode i dd(ah) 230 200 150 lsi rc osc. (128 khz) supply current in active halt mode i dd(ah) 105 8066 lsi rc osc. (128 khz) operating mode off i dd(ah) 35 1810 power-down mode i dd(ah) (1) data based on characterization results, not tested in production (2) configured by the regah bit in the clk_ickr register. (3) configured by the ahalt bit in the flash_cr1 register. 59/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
total current consumption in halt mode 10.3.2.4 table 29: total current consumption in halt mode at v dd = 5 v unit max at 125 c (1) max at 85 c (1) typ conditions parameter symbol a 105 75 63 flash in operating mode, hsi clock after wakeup supply current in halt mode i dd(h) 55 20 6.0 flash in power-down mode, hsi clock after wakeup (1) data based on characterization results, not tested in production table 30: total current consumption in halt mode at v dd = 3.3 v unit max at 125 c (1) max at 85 c (1) typ conditions parameter symbol a 100 75 60 flash in operating mode, hsi clock after wakeup supply current in halt mode i dd(h) 30 17 4.5 flash in power-down mode, hsi clock after wakeup (1) data based on characterization results, not tested in production low power mode wakeup times 10.3.2.5 table 31: wakeup times unit max (1) typ conditions parameter symbol s see note (2) - 0 to 16 mhz wakeup time from wait mode to run t wu(wfi) -0.56 f cpu = f master = 16 mhz mode (3) 2 (6) 1 (6) hsi (after flash in operating mode (5) mvr voltage regulator on (4) wakeup time active halt mode to run mode (3) t wu(ah) wakeup) -3 (6) hsi (after flash in power-down mvr voltage regulator wakeup time active halt mode to run wakeup) mode (5) on (4) mode (3) docid15590 rev 8 60/116 stm8s903k3 stm8s903f3 electrical characteristics
unit max (1) typ conditions parameter symbol -48 (6) hsi (after flash in operating mode (5) mvr voltage regulator off (4) wakeup time active halt mode to run mode (3) wakeup) -50 (6) hsi (after flash in power-down mvr voltage regulator wakeup time active halt mode to run wakeup) mode (5) off (4) mode (3) -52 flash in operating mode (5) wakeup time from halt mode to run t wu(h) -54 flash in power-down mode (5) mode (3) (1) data guaranteed by design, not tested in production. (2) t wu(wfi) = 2 x 1/f master + 6 x 1/f cpu. (3) measured from interrupt event to interrupt vector fetch. (4) configured by the regah bit in the clk_ickr register. (5) configured by the ahalt bit in the flash_cr1 register. (6) plus 1 lsi clock depending on synchronization. total current consumption and timing in forced reset state 10.3.2.6 table 32: total current consumption and timing in forced reset state unit max (1) typ conditions parameter symbol a - 400 v dd = 5 v supply current in reset state (2) i dd(r) - 300 v dd = 3.3 v s150 - reset pin release to vector fetch t resetbl (1) data guaranteed by design, not tested in production. (2) characterized with all i/os tied to v ss . current consumption of on-chip peripherals 10.3.2.7 subject to general operating conditions for v dd and t a . 61/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
hsi internal rc/f cpu = f master = 16 mhz, v dd = 5 v table 33: peripheral current consumption unit typ. parameter symbol a 210 tim1 supply current (1) i dd(tim1) 130 tim5 supply current (1) i dd(tim5) 50 tim6 timer supply current (1) i dd(tim6) 120 uart1 supply current (2) i dd(uart1) 45 spi supply current (2) i dd(spi) 65 i 2 c supply current (2) i dd(i 2 c) 1000 adc1 supply current when converting (3) i dd(adc1) (1) data based on a differential i dd measurement between reset configuration and timer counter running at 16 mhz. no ic/oc programmed (no i/o pads toggling). not tested in production. (2) data based on a differential i dd measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. no i/o pads toggling. not tested in production. (3) data based on a differential i dd measurement between reset configuration and continuous a/d conversions. not tested in production. current consumption curves 10.3.2.8 the following figures show typical current consumption measured with code executing in ram. figure 12: typ i dd(run) vs. v dd hse user external clock, f cpu = 16 mhz docid15590 rev 8 62/116 stm8s903k3 stm8s903f3 electrical characteristics
figure 13: typ i dd(run) vs. f cpu hse user external clock, v dd = 5 v figure 14: typ i dd(run) vs. v dd hsi rc osc, f cpu = 16 mhz 63/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
figure 15: typ i dd(wfi) vs. v dd hse user external clock, f cpu = 16 mhz figure 16: typ i dd(wfi) vs. f cpu hse user external clock, v dd = 5 v figure 17: typ i dd(wfi) vs. v dd hsi rc osc, f cpu = 16 mhz docid15590 rev 8 64/116 stm8s903k3 stm8s903f3 electrical characteristics
external clock sources and timing characteristics 10.3.3 hse user external clock subject to general operating conditions for v dd and t a . table 34: hse user external clock characteristics unit max min conditions parameter symbol mhz 16 0 user external clock source frequency f hse_ext v v dd + 0.3 v 0.7 x v dd oscin input pin high level voltage v hseh (1) 0.3 x v dd v ss oscin input pin low level voltage v hsel (1) a +1 -1 v ss < v in < v dd oscin input leakage current i leak_hse (1) data based on characterization results, not tested in production. figure 18: hse external clocksource hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 16 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...). table 35: hse oscillator characteristics unit max typmin conditions parameter symbol mhz 16 -1 external high speed oscillator frequency f hse 65/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3 v hseh v hsel exter nal cloc k source oscin f hse stm8
unit max typmin conditions parameter symbol k? - 220- feedback resistor r f pf 20 -- recommended load capacitance (2) c (1) ma 6 (startup) -- c = 20 pf, hse oscillator power consumption i dd(hse) 1.6 (stabilized) (3) f osc = 16 mhz 6 (startup) -- c = 10 pf, 1.2 (stabilized) (3) f osc =16 mhz ma/v - -5 oscillator transconductance g m ms - 1- v dd is stabilized startup time t su(hse) (4) (1) c is approximately equivalent to 2 x crystal cload. (2) the oscillator selection can be optimized in terms of supply current using a high quality resonator with small r m value. refer to crystal manufacturer for more details (3) data based on characterization results, not tested in production. (4) t su(hse) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. figure 19: hse oscillator circuit diagram hse oscillator critical g m equation g mcrit = (2 f hse ) 2 r m (2co + c) 2 docid15590 rev 8 66/116 stm8s903k3 stm8s903f3 electrical characteristics oscout oscin f hse to core c l1 c l2 r f stm8 resonator consumption control g m r m c m l m c o resonator
r m : notional resistance (see crystal specification) l m : notional inductance (see crystal specification) c m : notional capacitance (see crystal specification) co: shunt capacitance (see crystal specification) c l1 = c l2 = c: grounded external capacitance g m >> g mcrit internal clock sources and timing characteristics 10.3.4 subject to general operating conditions for v dd and t a . high speed internal rc oscillator (hsi) table 36: hsi oscillator characteristics unit max typ min conditions parameter symbol mhz - 16 - frequency f hsi % 1.0 (3) - - user-trimmed with clk_hsitrimr register for accuracy of hsi oscillator acc hsi given v dd and t a conditions (1) 1 - -1 v dd = 5 v, t a = 25c (2) accuracy of hsi oscillator (factory 2.0 - -2.0 v dd = 5 v, calibrated) 25 c t a 85 c 3.0 (2) - -3.0 (2) 2.95 v dd 5.5 v, -40 c t a 125 c s 1.0 (3) - - hsi oscillator wakeup time t su(hsi) including calibration a 250 (2) 170 - hsi oscillator power i dd(hsi) consumption (1) refer to application note. (2) data based on characterization results, not tested in production. (3) guaranteed by design, not tested in production. 67/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
figure 20: typical hsi frequency variation vs v dd @ 4 temperatures low speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . table 37: lsi oscillator characteristics unit max typ min parameter symbol khz 150 128 110 frequency f lsi s 7 - - lsi oscillator wake-up time t su(lsi) a - 5 - lsi oscillator power consumption i dd(lsi) figure 21: typical lsi frequency variation vs v dd @ 4 temperatures docid15590 rev 8 68/116 stm8s903k3 stm8s903f3 electrical characteristics
memory characteristics 10.3.5 ram and hardware registers table 38: ram and hardware registers unit min conditions parameter symbol v v it-max (2) halt mode (or reset) data retention mode (1) v rm (1) minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by design, not tested in production. (2) refer to the operating conditions section for the value of v it-max flash program memory/data eeprom memory table 39: flash program memory/data eeprom memory unit max typ min (1) conditions parameter symbol v5.5-2.95 f cpu 16 mhz operating voltage (all modes, execution/ write/erase) v dd ms 6.66- standard programming time (including erase) for t prog byte/word/block (1 byte/ 4 bytes/64 bytes) 3.333- fast programming time for 1 block (64 bytes) 3.333- erase time for 1 block (64 bytes) t erase cycles --10 k t a = +85 c erase/write cycles (2) (program memory) n rw -1 m 300 k t a = +125 c erase/write cycles (data memory) (2) years --20 t ret = 55c data retention (program and data memory) after 10k t ret erase/write cycles at t a = +55 c 69/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
unit max typ min (1) conditions parameter symbol --1 t ret = 85c data retention (data memory) after 300k erase/write cycles at t a = +125 c ma-2- supply current (flash programming or erasing i dd for 1 to 128 bytes) (1) data based on characterization results, not tested in production. (2) the physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. i/o port pin characteristics 10.3.6 general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor. table 40: i/o static characteristics unit max typ min conditions parameter symbol v 0.3 x v dd - -0.3 v v dd = 5 v input low level voltage v il v dd + 0.3 - 0.7 x v dd input high level voltage v ih mv - 700- hysteresis (1) v hys k 80 5530 v dd = 5 v, v in = v ss pull-up resistor r pu ns 35 (3) -- fast i/os load = 50 pf rise and fall time (10 % - 90 %) t r , t f 125 (3) -- standard and high sink i/os load = 50 pf 20 (3) -- fast i/os docid15590 rev 8 70/116 stm8s903k3 stm8s903f3 electrical characteristics
unit max typ min conditions parameter symbol load = 20 pf 50 (3) -- standard and high sink i/os load = 20 pf a 1 (2) -- v ss v in v dd digital input leakage current i lkg na 250 (2) -- v ss v in v dd analog input leakage current i lkg ana a 1 (2) -- injection current 4 ma leakage current in adjacent i/o i lkg(inj) (1) hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested in production. (2) data based on characterisation results, not tested in production. (3) data guaranteed by design. figure 22: typical v il and v ih vs v dd @ 4 temperatures 71/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
figure 23: typical pull-up resistance vs v dd @ 4 temperatures figure 24: typical pull-up current vs v dd @ 4 temperatures table 41: output driving current (standard ports) unit max min conditions parameter symbol v 2.0- i io = 10 ma, v dd = 5 v output low level with 8 pins sunk v ol 1.0 (1) - i io = 4 ma, v dd = 3.3 v output low level with 4 pins sunk -2.8 i io = 10 ma, v dd = 5 v output high level with 8 pins sourced v oh docid15590 rev 8 72/116 stm8s903k3 stm8s903f3 electrical characteristics
unit max min conditions parameter symbol - 2.1 (1) i io = 4 ma, v dd = 3.3 v output high level with 4 pins sourced (1) data based on characterization results, not tested in production table 42: output driving current (true open drain ports) unit max conditions parameter symbol v 1 .0 i io = 10 ma, v dd = 5 v output low level with 2 pins sunk v ol 1.5 (1) i io = 10 ma, v dd = 3.3 v output low level with 2 pins sunk v ol 2.0 (1) i io = 20 ma, v dd = 5 v output low level with 2 pins sunk v ol (1) data based on characterization results, not tested in production table 43: output driving current (high sink ports) unit max min conditions parameter symbol v0.8- i io = 10 ma, v dd = 5 v output low level with 8 pins sunk v ol v 1.0 (1) - i io = 10 ma, v dd = 3.3 v output low level with 4 pins sunk v ol 1.5 (1) - i io = 20 ma, v dd = 5 v output low level with 4 pins sunk -4.0 i io = 10 ma, v dd = 5 v output high level with 8 pins sourced v oh - 2.1 (1) i io = 10 ma, v dd = 3.3 v output high level with 4 pins sourced - 3.3 (1) i io = 20 ma, v dd = 5 v output high level with 4 pins sourced (1) data based on characterization results, not tested in production 73/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
figure 25: typ. v ol @ v dd = 5 v (standard ports) figure 26: typ. v ol @ v dd = 3.3 v (standard ports) docid15590 rev 8 74/116 stm8s903k3 stm8s903f3 electrical characteristics
figure 27: typ. v ol @ v dd = 5 v (true open drain ports) figure 28: typ. v ol @ v dd = 3.3 v (true open drain ports) 75/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
figure 29: typ. v ol @ v dd = 5 v (high sink ports) figure 30: typ. v ol @ v dd = 3.3 v (high sink ports) docid15590 rev 8 76/116 stm8s903k3 stm8s903f3 electrical characteristics
figure 31: typ. v dd - v oh @ v dd = 5 v (standard ports) figure 32: typ. v dd - v oh @ v dd = 3.3 v (standard ports) 77/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
figure 33: typ. v dd - v oh @ v dd = 5 v (high sink ports) figure 34: typ. v dd - v oh @ v dd = 3.3 v (high sink ports) reset pin characteristics 10.3.7 subject to general operating conditions for v dd and t a unless otherwise specified. table 44: nrst pin characteristics unit max typ min conditions parameter symbol v 0.3 x v dd - -0.3 nrst input low v il(nrst) level voltage (1) docid15590 rev 8 78/116 stm8s903k3 stm8s903f3 electrical characteristics
unit max typ min conditions parameter symbol v dd + 0.3 - 0.7 x v dd i ol =2 ma nrst input high v ih(nrst) level voltage (1) 0.5 - - nrst output low v ol(nrst) level voltage (1) k 80 55 30 nrst pull-up r pu(nrst) resistor (2) ns 75 - - nrst input filtered t i fp(nrst) pulse (3) - - 500 nrst input not t in fp(nrst) filtered pulse (3) s - - 20 nrst output pulse (3) t op(nrst) (1) data based on characterization results, not tested in production. (2) the r pu pull-up equivalent resistor is based on a resistive transistor (3) data guaranteed by design, not tested in production. figure 35: typical nrst v il and v ih vs v dd @ 4 temperatures 79/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
figure 36: typical nrst pull-up resistance vs v dd @ 4 temperatures figure 37: typical nrst pull-up current vs v dd @ 4 temperatures the reset network shown in the following figure protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below v il(nrst) max. (see table 40: i/o static characteristics ), otherwise the reset is not taken into account internally. for power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. if nrst signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. minimum recommended capacity is 100 nf. docid15590 rev 8 80/116 stm8s903k3 stm8s903f3 electrical characteristics
figure 38: recommended reset pin protection spi serial peripheral interface 10.3.8 unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 45: spi characteristics unit max min conditions (1) parameter symbol mhz 80 master mode spi clock frequency f sck 1/ t c(sck) mhz 7 (2) 0 spi clock frequency f sck 1/ t c(sck) f sck 1/ t c(sck) ns 25 capacitive load: c = 30 pf spi clock rise and fall time t r(sck) t f(sck) 4 x t master slave mode nss setup time t su(nss) (3) 70 slave mode nss hold time t h(nss) (3) t sck / 2 +15 t sck / 2 - 15 master mode sck high and low time t w(sckh) (3) t w(sckl) (3) 5 master mode data input setup time t su(mi) (3) t su(si) (3) 5 slave mode 7 master mode data input hold time t h(mi) (3) t h(si) (3) 10 slave mode 81/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3 exter nal reset circuit (optional) 0.1 f nrst vdd rpu filter inter nal reset stm8
unit max min conditions (1) parameter symbol 3 x t master slave mode data output access time t a(so) (3) (4) 25 slave mode data output disable time t dis(so) (3) (5) 65 (2) slave mode (after enable edge) data output valid time t v(so) (3) 30 master mode (after enable edge) data output valid time t v(mo) (3) 27 (2) slave mode (after enable edge) data output hold time t h(so) (3) 11 (2) master mode (after enable edge) data output hold time t h(mo) (3) (1) parameters are given by selecting 10 mhz i/o output frequency. (2) data characterization in progress. (3) values based on design simulation and/or characterization results, and not tested in production. (4) min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. (5) min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z. docid15590 rev 8 82/116 stm8s903k3 stm8s903f3 electrical characteristics
figure 39: spi timing diagram - slave mode and cpha = 0 figure 40: spi timing diagram - slave mode and cpha = 1 1. measurement points are made at cmos levels: 0.3 vdd and 0.7 vdd. 83/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3 ai14135 sck input c p h a =1 m o s i i n p u t m i s o o u t p u t c p h a =1 m s b o u t m s b i n b i t 6 o u t l s b i n l s b o u t c p o l = 0 c p o l = 1 b i t 1 i n t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input ai14134 sck input c p h a = 0 m o s i i n p u t m i s o o u t p u t c p h a = 0 m s b o u t m s b i n b i t 6 o u t l s b i n l s b o u t c p o l = 0 c p o l = 1 b i t 1 i n n s s input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si)
figure 41: spi timing diagram - master mode (1) 1. measurement points are made at cmos levels: 0.3 vdd and 0.7 vdd. i 2 c interface characteristics 10.3.9 table 46: i 2 c characteristics unit fast mode i 2 c (1) standard mode i 2 c parameter symbol max (2) min (2) max (2) min (2) s -1.3- 4.7 scl clock low time t w(scll) -0.6- 4.0 scl clock high time t w(sclh) ns - 100 - 250 sda setup time t su(sda) 900 (3) 0 (4) - 0 (3) sda data hold time t h(sda) 300 - 1000 - sda and scl rise time t r(sda) t r(scl) 300 - 300 - sda and scl fall time t f(sda) t f(scl) s -0.6- 4.0 start condition hold time t h(sta) -0.6- 4.7 repeated start condition setup time t su(sta) docid15590 rev 8 84/116 stm8s903k3 stm8s903f3 electrical characteristics ai14136b sck output c p h a = 0 m o s i out u t m i s o in p u t c p h a = 0 m s bin m s b out b i t 6 in l s b out l s b in c p o l = 0 c p o l = 1 b i t 1 out n s s input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck output c p h a =1 c p h a =1 c p o l = 0 c p o l = 1 t su(mi) t v(mo) t h(mo)
unit fast mode i 2 c (1) standard mode i 2 c parameter symbol max (2) min (2) max (2) min (2) -0.6- 4.0 stop condition setup time t su(sto) s-1.3- 4.7 stop to start condition time (bus free) t w(sto:sta) pf 400 - 400 - capacitive load for each bus line c b (1) f master , must be at least 8 mhz to achieve max fast i 2 c speed (400khz) (2) data based on standard i 2 c protocol requirement, not tested in production (3) the maximum hold time of the start condition has only to be met if the interface does not stretch the low time (4) the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl figure 42: typical application with i 2 c bus and timing diagram 1. measurement points are made at cmos levels: 0.3 x vdd and 0.7 x vdd. 10-bit adc characteristics 10.3.10 subject to general operating conditions for v dd , f master , and t a unless otherwise specified. table 47: adc characteristics unit maxtyp min conditions parameter symbol mhz4-1 v dd =2.95 to 5.5 v adc clock frequency f adc 85/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3 t f ( s d a ) t r ( s d a ) t s u (s d a ) t h ( s d a ) t f( s c l ) t r ( s c l ) t w ( s c ll ) t w ( s c l h ) t h ( s t a ) t s u ( s t o ) t s u ( s t a) t w ( s t o :s t a ) sd a scl 4 . 7 k ? s d a s c l 1 0 0 ? 1 0 0 ? 4. 7 k ? i 2 c b u s st ar t st ar t st op repea ted st ar t stm8s v dd v dd ai17490
unit maxtyp min conditions parameter symbol 6-1 v dd =4.5 to 5.5 v vv dd -v ss conversion voltage range (1) v ain v1.25 1.22 1.19 v dd =2.95 to 5.5 v internal bandgap reference voltage v bgref pf-3- internal sample and hold capacitor c adc s-0.75- f adc = 4 mhz minimum sampling time t s (1) -0.5- f adc = 6 mhz s- 7 - wake-up time from standby t stab s 3.5 f adc = 4 mhz minimum total conversion time (including sampling time, 10-bit resolution) t conv s 2.33 f adc = 6 mhz 1/f adc 14 (1) during the sample time the input capacitance c ain (3 pf max) can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depend on programming. table 48: adc accuracy with r ain < 10 k , v dd = 5 v unit max (1) typ conditions parameter symbol lsb 3.5 1.6 f adc = 2 mhz total unadjusted error (2) |e t | 42.2 f adc = 4 mhz 4.5 2.4 f adc = 6 mhz 2.5 1.1 f adc = 2 mhz offset error (2) |e o | 31.5 f adc = 4 mhz 31.8 f adc = 6 mhz 31.5 f adc = 2 mhz gain error (2) |e g | 32.1 f adc = 4 mhz 42.2 f adc = 6 mhz 1.5 0.7 f adc = 2 mhz differential linearity error (2) |e d | 1.5 0.7 f adc = 4 mhz docid15590 rev 8 86/116 stm8s903k3 stm8s903f3 electrical characteristics
unit max (1) typ conditions parameter symbol 1.5 0.7 f adc = 6 mhz 1.5 0.6 f adc = 2 mhz integral linearity error (2) |e l | 20.8 f adc = 4 mhz 20.8 f adc = 6 mhz (1) data based on characterisation results, not tested in production. (2) adc accuracy vs. negative injection current: injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in the i/o port pin characteristics section does not affect the adc accuracy. table 49: adc accuracy with r ain < 10 k r ain , v dd = 3.3 v unit max (1) typ conditions parameter symbol lsb 3.5 1.6 f adc = 2 mhz total unadjusted error |e t | 41.9 f adc = 4 mhz 2.51 f adc = 2 mhz offset error |e o | 2.5 1.5 f adc = 4 mhz 31.3 f adc = 2 mhz gain error |e g | 32 f adc = 4 mhz 10.7 f adc = 2 mhz differential linearity error |e d | 1.5 0.7 f adc = 4 mhz 1.5 0.6 f adc = 2 mhz integral linearity error |e l | 20.8 f adc = 4 mhz (1) data based on characterisation results, not tested in production. 87/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
figure 43: adc accuracy characteristics 1. example of an actual transfer curve. 2. the ideal transfer curve 3. end point correlation line e t = total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o = offset error: deviation between the first actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = differential linearity error: maximum deviation between actual steps and the ideal one. e l = integral linearity error: maximum deviation between any actual transition and the end point correlation line. figure 44: typical application with adc docid15590 rev 8 88/116 stm8s903k3 stm8s903f3 electrical characteristics stm8 10-bit a/d con v ersion r ain c ain v ain ainx v dd v t 0.6 v v t 0.6 v i l 1 a c adc
emc characteristics 10.3.11 susceptibility tests are performed on a sample basis during product characterization. functional ems (electromagnetic susceptibility) 10.3.11.1 while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). ? fesd: functional electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 61000-4-2 standard. ? ftb: a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test conforms with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709 (emc design guide for stmicrocontrollers). designing hardened software to avoid noise problems 10.3.11.2 emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. prequalification trials most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring. see application note an1015 (software techniques for improving microcontroller emc performance). table 50: ems data level/ class conditions parameter symbol 2/b (1) v dd = 3.3 v, t a = 25 c, f master = 16 mhz (hsi clock), conforming to iec 61000-4-2 voltage limits to be applied on any i/o pin to induce a functional disturbance v fesd 4/a (1) v dd = 3.3 v, t a = 25 c ,f master = 16 mhz (hsi clock),conforming to iec 61000-4-4 fast transient voltage burst limits to be applied through 100 pf on v dd v eftb and v ss pins to induce a functional disturbance 89/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
(1) data obtained with hsi clock configuration, after applying hw recommendations described in an2860 (emc guidelines for stm8s microcontrollers). electromagnetic interference (emi) 10.3.11.3 based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae iec 61967-2 which specifies the board and the loading of each pin. table 51: emi data unit conditions parameter symbol max f hse /f cpu (1) monitored frequency band general conditions 16 mhz/ 16 mhz 16 mhz/ 8 mhz dbv 5 5 0.1 mhz to v dd = 5 v t a = 25 c peak level s emi 30 mhz lqfp32 package 5 4 30 mhz to conforming to sae iec 61967-2 130 mhz 5 5 130 mhz to 1 ghz 2.5 2.5 sae emi level sae emi level (1) data based on characterisation results, not tested in production. absolute maximum ratings (electrical sensitivity) 10.3.11.4 based on three different tests (esd, dlu and lu) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) 10.3.11.5 electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). one model can be simulated: docid15590 rev 8 90/116 stm8s903k3 stm8s903f3 electrical characteristics
human body model. this test conforms to the jesd22-a114a/a115a standard. for more details, refer to the application note an1181. table 52: esd absolute maximum ratings unit maximum value (1) class conditions ratings symbol v 4000 a t a = 25c, conforming to electrostatic discharge v esd(hbm) jesd22-a114 voltage (human body model) 1000 iv t a lqfp32 package = electrostatic discharge v esd(cdm) 25c, conforming to voltage sd22-c101 (charge device model) (1) data based on characterization results, not tested in production static latch-up 10.3.11.6 two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage (applied to each power supply pin) ? a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. table 53: electrical sensitivities class (1) conditions parameter symbol a t a = 25 c static latch-up class lu a t a = 85 c a t a = 125 c (1) class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 91/116 docid15590 rev 8 electrical characteristics stm8s903k3 stm8s903f3
package information 11 in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. 32-pin lqfp package mechanical data 11.1 figure 45: 32-pin low profile quad flat package (7 x 7) table 54: 32-pin low profile quad flat package mechanical data inches (1) mm dim. max typ min max typ min 0.0630 1.600 a 0.0059 0.0020 0.150 0.050 a1 0.0571 0.0551 0.0531 1.450 1.400 1.350 a2 0.0177 0.0146 0.0118 0.450 0.370 0.300 b 0.0079 0.0035 0.200 0.090 c 0.3622 0.3543 0.3465 9.200 9.000 8.800 d 0.2835 0.2756 0.2677 7.200 7.000 6.800 d1 docid15590 rev 8 92/116 stm8s903k3 stm8s903f3 package information 5v_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 16 17 24 25 b 32 1 pin 1 identification 8 9
inches (1) mm dim. max typ min max typ min 0.2205 5.600 d3 0.3622 0.3543 0.3465 9.200 9.000 8.800 e 0.2835 0.2756 0.2677 7.200 7.000 6.800 e1 0.2205 5.600 e3 0.0315 0.800 e 0.0295 0.0236 0.0177 0.750 0.600 0.450 l 0.0394 1.000 l1 7.0 3.5 0.0 7.0 3.5 0.0 k 0.0039 0.100 ccc (1) values in inches are converted from mm and rounded to 4 decimal digits 93/116 docid15590 rev 8 package information stm8s903k3 stm8s903f3
32-lead ufqfpn package mechanical data 11.2 figure 46: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of the ufqfpn package. it is recommended to connect and solder this backside pad to pcb ground. 4. dimensions are in millimeters. table 55: 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data inches (1) mm dim. max typ min max typ min 0.0236 0.0217 0.0197 0.600 0.550 0.500 a 0.0020 0.0008 0.050 0.020 0 a1 0.0079 0.200 a3 docid15590 rev 8 94/116 stm8s903k3 stm8s903f3 package information a ob8_me
inches (1) mm dim. max typ min max typ min 0.0118 0.0098 0.0071 0.300 0.250 0.180 b 0.2028 0.1969 0.1909 5.150 5.000 4.850 d 0.1457 0.1260 3.700 3.450 3.200 d2 0.2028 0.1969 0.1909 5.150 5.000 4.850 e 0.1457 0.1358 0.1260 3.700 3.450 3.200 e2 0.0197 0.500 e 0.0197 0.0157 0.0118 0.500 0.400 0.300 l 0.0031 0.080 ddd (1) values in inches are converted from mm and rounded to 4 decimal digits. 20-lead ufqfpn package mechanical data 11.3 figure 47: 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) 95/116 docid15590 rev 8 package information stm8s903k3 stm8s903f3 103_a0a5_me 11 15 16 20 1 5 d e b e e a1 a ddd l2 10 l1 a3 l3 l4 d e t op view side view bo tt om view pin 1
1. drawing is not to scale. table 56: 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data inches (1) mm dim. max typ min max typ min 0.1181 3.000 d 0.1181 3.000 e 0.0236 0.0217 0.0197 0.600 0.550 0.500 a 0.0020 0.0008 0.0000 0.050 0.020 0.000 a1 0.0060 0.152 a3 0.0197 0.500 e 0.0236 0.0217 0.0197 0.600 0.550 0.500 l1 0.0157 0.0138 0.0118 0.400 0.350 0.300 l2 0.0059 0.150 l3 0.0079 0.200 l4 0.0118 0.0098 0.0071 0.300 0.250 0.180 b 0.0020 0.050 ddd (1) values in inches are converted from mm and rounded to 4 decimal digits. docid15590 rev 8 96/116 stm8s903k3 stm8s903f3 package information
ufqfpn recommended footprint 11.4 figure 48: recommended footprint for on-board emulation 1. drawing is not to scale 97/116 docid15590 rev 8 package information stm8s903k3 stm8s903f3 b o t t o m v i e w 4 m m [ 0 . 1 5 7 " ] 4 m m [ 0 . 1 5 7 " ] 0 . 5 m m 0 . 5 m m 0 . 3 m m [ 0 . 0 1 2 " ] 0 . 9 m m [ 0 . 0 3 5 " ] 0 . 8 m m [ 0 . 0 3 2 " ] 1 . 6 5 m m [ 0 . 0 6 5 " ] ai15319
figure 49: recommended footprint without on-board emulation 1. drawing is not to scale 2. dimensions are in millimeters sdip32 package mechanical data 11.5 figure 50: 32-lead shrink plastic dip (400 ml) package docid15590 rev 8 98/116 stm8s903k3 stm8s903f3 package information 76_me a2 a1 a l b1 b e ea d d 1 32 16 17 e1 e c eb
table 57: 32-lead shrink plastic dip (400 ml) package mechanical data inches (1) mm dim. max typ min max typ min 0.2000 0.1480 0.1400 5.080 3.759 3.556 a 0.0200 0.508 a1 0.1800 0.1400 0.1200 4.572 3.556 3.048 a2 0.0230 0.0180 0.0140 0.584 0.457 0.356 b 0.0550 0.0400 0.0300 1.397 1.016 0.762 b1 0.0140 0.0100 0.0079 0.356 0.254 0.203 c 1.1201 1.1000 1.0799 28.450 27.940 27.430 d 0.4350 0.4098 0.3900 11.050 10.410 9.906 e 0.3700 0.3500 0.3000 9.398 8.890 7.620 e1 0.0700 1.778 e 0.4000 10.160 ea 0.5000 12.700 eb 0.1500 0.1200 0.1000 3.810 3.048 2.540 l (1) values in inches are converted from mm and rounded to 4 decimal digits 99/116 docid15590 rev 8 package information stm8s903k3 stm8s903f3
20-pin tssop package mechanical data 11.6 figure 51: 20-pin, 4.40 mm body, 0.65 mm pitch table 58: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data inches (1) mm dim. max typ min max typ min 0.0472 1.200 a 0.0059 0.0020 0.150 0.050 a1 0.0413 0.0394 0.0315 1.050 1.000 0.800 a2 0.0118 0.0075 0.300 0.190 b 0.0079 0.0035 0.200 0.090 c 0.2598 0.2559 0.2520 6.600 6.500 6.400 d 0.2598 0.2520 0.2441 6.600 6.400 6.200 e 0.1772 0.1732 0.1693 4.500 4.400 4.300 e1 0.0256 0.650 e 0.0295 0.0236 0.0177 0.750 0.600 0.450 l 0.0394 1.000 l1 docid15590 rev 8 100/116 stm8s903k3 stm8s903f3 package information y a_me 1 20 cp c l e e1 d a2 a k e b 10 11 a1 l1 aaa
inches (1) mm dim. max typ min max typ min 8.0 0.0 8.0 0.0 k 0.0039 0.100 aaa (1) values in inches are converted from mm and rounded to 4 decimal digits 20-pin so package mechanical data 11.7 figure 52: 20-lead, plastic small outline (300 mils) package table 59: 20-lead, plastic small outline (300 mils) mechanical data inches (1) mm dim. max typ min max typ min 0.1043 0.0925 2.650 2.350 a 0.0118 0.0039 0.300 0.100 a1 0.0201 0.013 0.510 0.330 b 0.0126 0.0091 0.320 0.230 c 0.5118 0.4961 13.000 12.600 d 0.2992 0.2913 7.600 7.400 e 0.0500 1.270 e 101/116 docid15590 rev 8 package information stm8s903k3 stm8s903f3 e 20 e d c h 1 10 11 b z7_me a1 l a1 k h x 45 a ddd
inches (1) mm dim. max typ min max typ min 0.4193 0.3937 10.650 10.000 h 0.0295 0.0098 0.750 0.250 h 0.0500 0.0157 1.270 0.400 l 8.0 0.0 8.0 0.0 k 0.0039 0.100 ddd (1) values in inches are converted from mm and rounded to 4 decimal digits thermal characteristics 11.8 the maximum chip junction temperature (t j max ) must never exceed the values given in operating conditions . the maximum chip-junction temperature, t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: ? t amax is the maximum ambient temperature in c ? ja is the package junction-to-ambient thermal resistance in c/w ? p dmax is the sum of p intmax and p i/omax (pdmax = p intmax + p i/omax ) ? p intmax is the product of i dd andv dd , expressed in watts. this is the maximum chip internal power. ? p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd -v oh) *i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. table 60: thermal characteristics unit value parameter (1) symbol c/w 110 thermal resistance junction-ambient tssop20 - 4 x 4 mm ja c/w 20 thermal resistance junction-ambient so20w - 300 mils ja docid15590 rev 8 102/116 stm8s903k3 stm8s903f3 package information
unit value parameter (1) symbol c/w 101 thermal resistance junction-ambient ufqfpn20 - 3 x 3 mm ja c/w 60 thermal resistance junction-ambient lqfp32 - 7 x 7 mm ja c/w 38 thermal resistance junction-ambient ja ufqfpn32 - 5 x 5 mm c/w 60 thermal resistance junction-ambient ja sdip32 - 400 mils (1) thermal resistances are based on jedec jesd51-2 with 4-layer pcb in a natural convection environment. reference document 11.8.1 jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. selecting the product temperature range 11.8.2 when ordering the microcontroller, the temperature range is specified in the order code. the following example shows how to calculate the temperature range needed for a given application. assuming the following application conditions: ? maximum ambient temperature t amax = 75 c (measured according to jesd51-2) ? i ddmax = 8 ma, v dd = 5 v ? maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 8 ma x 5 v = 400 mw amax ? p dmax = 400 mw + 64 mw thus: p dmax = 464 mw t jmax for lqfp32 can be calculated as follows, using the thermal resistance ja : t jmax = 75 c + (60 c/w x 464 mw) = 75 c + 27.8 c = 102.8 c this is within the range of the suffix 6 version parts (-40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 6. 103/116 docid15590 rev 8 package information stm8s903k3 stm8s903f3
ordering information 12 figure 53: stm8s903k3/f3 ordering information scheme 1. a dedicated ordering information scheme will be released if, in the future, memory programming service (fastrom) is required. the letter "p" will be added after stm8s. three unique letters identifying the customer application code will also be visible in the codification. example: stm8sp903k3mactr. 2. ufqfpn, tssop, and so packages. 3. lqfp package. for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you. stm8s903k3/f3 fastrom microcontroller option list 12.1 (last update: april 2010) docid15590 rev 8 104/116 stm8s903k3 stm8s903f3 ordering information product class pin count k = 32 pins p ac kage type 1 t = lqfp u = ufqfpn example: sub-f amily type 903 = 903 sub-f amily f amily type s = standard t emper ature r ange 3 = -40 c to 125 c 6 = -40 c to 85 c prog r am memor y siz e 3 = 8 kb ytes p ac king no char acter = t r a y or tube tr = t ape and reel stm8 s 903 k 3 t 6 tr stm8 microcontroller b = sdip p = tssop f = 20 pins m = so p ac kage pitch blank = 0.5 or 0.65 mm (2) c = 0.8 mm (3)
........................................................................................................... customer ........................................................................................................... address ........................................................................................................... contact ........................................................................................................... phone no. fastrom code name is assigned by stmicroelectronics reference fastrom code preferable format for programing code is .hex (.s19 is accepted) if data eeprom programing is required, a seperate file must be sent with the requested data. important: see the option byte section in the datasheet for authorized option byte combinations and a detailed explanation. do not use more than one remapping option in the same port. it is forbidden to enable both afr1 and afr0. device type/memory size/package 8 kbyte fastrom device [ ] stm8s903f3 tssop20 [ ] stm8s903f3 so20 [ ] stm8s903f3 ufqfpn20 [ ] stm8s903k3 lqfp32 [ ] stm8s903k3 ufqfpn32 conditioning (check only one option) [ ] tape & reel or [ ] tray special marking (check only one option) [ ] no [ ] yes authorized characters are letters, digits, '.', '-', '/' and spaces only. maximum character counts are: lqfp32: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _" tssop20: 1 line of 10 characters max: "_ _ _ _ _ _ _ _ _ _" so20: 1 line of 13 characters max: "_ _ _ _ _ _ _ _ _ _ _ _ _" ufqfpn32: 1 line of 7 characters max: "_ _ _ _ _ _ _" ufqfpn20: 1 line of 4 characters max: "_ _ _ _ " three characters are reserved for code identification. temperature range [ ] -40c to +85c or [ ] -40c to +125c 105/116 docid15590 rev 8 ordering information stm8s903k3 stm8s903f3
padding value for unused program memory (check only one option) fixed value [ ]0xff trap instruction opcode [ ]0x83 illegal opcode (causes a reset when executed) [ ]0x75 opt0 memory readout protection (check only one option) [ ] disable or [ ] enable opt1 user boot code area (ubc) 0x(_ _) fill in the hexadecimal value, refering to the datasheet and the binary format below. [ ] 0: reset ubc, bit0 [ ] 1: set [ ] 0: reset ubc bit1 [ ] 1: set [ ] 0: reset ubc bit2 [ ] 1: set [ ] 0: reset ubc bit3 [ ] 1: set [ ] 0: reset ubc bit4 [ ] 1: set [ ] 0: reset ubc bit5 [ ] 1: set [ ] 0: reset ubc bit6 [ ] 1: set [ ] 0: reset ubc bit7 [ ] 1: set note: if the ubc area is not used, please select all bits at reset states. opt2 alternate function remapping for stm8s903k3 do not use more than one remapping option in the same port. docid15590 rev 8 106/116 stm8s903k3 stm8s903f3 ordering information
[ ] 00: remapping options inactive. default alternate functions used. refer to pinout description. afr1, afr0 (check only one option) [ ] 01: port c5 alternate function = tim5_ch1, port c6 alternate function = tim1_ch1, and port c7 alternate function = tim1_ch2. [ ] 10: port a3 alternate function = spi_nss and port d2 alternate function = tim5_ch3. [ ] 11: port d2 alternate function = tim5_ch3, port c5 alternate function = tim5_ch1, port c6 alternate function = tim1_ch1, port c7 alternate function = tim1_ch2, port c2 alternate function = tim1_ch3n, port c1 alternate function = tim1_ch2n, port e5 alternate function = tim1_ch1n, port a3 alternate function = uart1_tx, and port f4 alternate function = uart1_rx. [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. afr2 (check only one option) [ ] 1: port c4 alternate function = ain2, port d2 alternate function = ain3, port d4 alternate function = uart1_ck. [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. afr3 (check only one option) [ ] 1: port c3 alternate function = tli. [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. afr4 (check only one option) [ ] 1: port b4 alternate function = adc_etr, port b5 alternate function = tim1_bkin. [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. afr5 (check only one option) [ ] 1: port d0 alternate function = clk_cco. [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. afr6 (check only one option) [ ] 1: port d7 alternate function = tim1_ch4. [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. afr7 (check only one option) [ ] 1: port c3 alternate function = tim1_ch1n, port c4 alternate function = tim1_ch2n. 107/116 docid15590 rev 8 ordering information stm8s903k3 stm8s903f3
opt2 alternate function remapping for stm8s903f3 do not use more than one remapping option in the same port. [ ] 00: remapping options inactive. default alternate functions used. refer to pinout description. afr1, afr0 (check only one option) [ ] 01: port c5 alternate function = tim5_ch1, port c6 alternate function = tim1_ch1, and port c7 alternate function = tim1_ch2. [ ] 10: port a3 alternate function = spi_nss and port d2 alternate function = tim5_ch3. [ ] 11: port d2 alternate function = tim5_ch3, port c5 alternate function = tim5_ch1, port c6 alternate function = tim1_ch1, port c7 alternate function = tim1_ch2, port e5 alternate function = tim1_ch1n, port a3 alternate function = uart1_tx, and port f4 alternate function = uart1_rx. reserved afr2 [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. afr3 (check only one option) [ ] 1: port c3 alternate function = tli. [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. afr4 (check only one option) [ ] 1: port b4 alternate function = adc_etr, port b5 alternate function = tim1_bkin. reserved afr5 reserved afr6 [ ] 0: remapping option inactive. default alternate functions used. refer to pinout description. afr7 (check only one option) [ ] 1: port c3 alternate function = tim1_ch1n, port c4 alternate function = tim1_ch2n. opt3 watchdog [ ] 0: no reset generated on halt if wwdg active wwdg_halt (check only one option) [ ] 1: reset generated on halt if wwdg active [ ] 0: wwdg activated by software wwdg_hw (check only one option) [ ] 1: wwdg activated by hardware docid15590 rev 8 108/116 stm8s903k3 stm8s903f3 ordering information
[ ] 0: iwdg activated by software iwdg_hw (check only one option) [ ] 1: iwdg activated by hardware [ ] 0: lsi clock is not available as cpu clock source lsi_en (check only one option) [ ] 1: lsi clock is available as cpu clock source [ ] 0: 3-bit trimming supported in clk_hsitrimr register hsitrim (check only one option) [ ] 1: 4-bit trimming supported in clk_hsitrimr register opt4 wakeup [ ] for 16 mhz to 128 khz prescaler prsc (check only one option) [ ] for 8 mhz to 128 khz prescaler [ ] for 4 mhz to 128 khz prescaler [ ] lsi clock source selected for awu ckawusel (check only one option) [ ] hse clock with prescaler selected as clock source for for awu [ ] external crystal connected to oscin/oscout extclk (check only one option) [ ] external clock signal on oscin opt5 crystal oscillator stabilization hsecnt (check only one option) [ ] 2048 hse cycles [ ] 128 hse cycles [ ] 8 hse cycles [ ] 0.5 hse cycles opt6 is reserved ........................................................................................................... comments: ........................................................................................................... supply operating range in the application: ........................................................................................................... notes: 109/116 docid15590 rev 8 ordering information stm8s903k3 stm8s903f3
stm8 development tools 13 development tools for the stm8 microcontrollers include the full-featured stice emulation system supported by a complete software tool package including c compiler, assembler and integrated development environment with high-level language debugger. in addition, the stm8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. emulation and in-circuit debugging tools 13.1 the stice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. in addition, stm8 application development is supported by a low-cost in-circuit debugger/programmer. the stice is the fourth generation of full featured emulators from stmicroelectronics. it offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. in addition, stice offers in-circuit debugging and programming of stm8 microcontrollers via the stm8 single wire interface module (swim), which allows non-intrusive debugging of an application while it runs on the target microcontroller. for improved cost effectiveness, stice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future st microcontrollers. stice key features ? occurrence and time profiling and code coverage (new features) ? advanced breakpoints with up to 4 levels of conditions ? data breakpoints ? program and data trace recording up to 128 kb records ? read/write on the fly of memory during emulation ? in-circuit debugging/programming via swim protocol ? 8-bit probe analyzer ? 1 input and 2 output triggers ? power supply follower managing application voltages between 1.62 to 5.5 v ? modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements ? supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8. software tools 13.2 stm8 development tools are supported by a complete, free software package from stmicroelectronics that includes st visual develop (stvd) ide and the st visual programmer (stvp) software interface. stvd provides seamless integration of the cosmic and raisonance c compilers for stm8, which are available in a free version that outputs up to 16 kbytes of code. docid15590 rev 8 110/116 stm8s903k3 stm8s903f3 stm8 development tools
stm8 toolset 13.2.1 stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com/mcu. this package includes: st visual develop C full-featured integrated development environment from st, featuring ? seamless integration of c and asm toolsets ? full-featured debugger ? project management ? syntax highlighting editor ? integrated programming interface ? support of advanced emulation features for stice such as code profiling and coverage st visual programmer (stvp) C easy-to-use, unlimited graphical interface allowing read, write and verify of your stm8 microcontrollers flash program memory, data eeprom and option bytes. stvp also offers project mode for saving programming configurations and automating programming sequences. c and assembly toolchains 13.2.2 control of c and assembly toolchains is seamlessly integrated into the stvd integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. available toolchains include: ? cosmic c compiler for stm8 C available in a free version that outputs up to 16 kbytes of code. for more information, see www.cosmic-software.com. ? raisonance c compiler for stm8 C available in a free version that outputs up to 16 kbytes of code. for more information, see www.raisonance.com. ? stm8 assembler linker C free assembly toolchain included in the stvd toolset, which allows you to assemble and link your application source code. programming tools 13.3 during the development cycle, stice provides in-circuit programming of the stm8 flash microcontroller on your application board via the swim protocol. additional tools are to include a low-cost in-circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming your stm8. for production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the stm8 family. 111/116 docid15590 rev 8 stm8 development tools stm8s903k3 stm8s903f3
revision history 14 table 61: document revision history changes revision date initial revision 1 30-apr-2009 added bullet point concerning unique identifier to features section on cover page. 2 03-jun-2009 highlighted internal reference voltage in analog-to-digital converter (adc1) section. updated wpu and pp status of pb5/12c_sda[tim1_bkin] and pb4/12c_scl[adc_etr] pins in pin description . updated figure 7: memory map . added unique id section. added tbd values to table 45: spi characteristics . added max values to table 48: adc accuracy with rain < 10 k , vdd= 5 v and table 49: adc accuracy with rain < 10 k rain, vdd = 3.3 v . added so20w, tssop20, sdip32, and ufqfpn32 packages. 3 22-apr-2010 added stm8s903f3 part number. updated datasheet status to full datasheet. updated definition of alternate function remapping option in table 4: legend/abbreviations for pinout tables . updated px_idr reset value in table 7: i/o port hardware register map table. removed esr low limit and update high limit for cext conditions in table 21: general operating conditions . operating conditions : updated vcap and esr low limit, added esl parameter, as well as p d in table 21: general operating conditions . functional ems (electromagnetic susceptibility) : changed esd to fesd (functional esd); added name of an1709; replaced iec 1000 with iec 61000. designing hardened software to avoid noise problems replaced iec 1000 with iec 61000, added title of an1015, and added footnote to table 50: ems data . electromagnetic interference (emi) replaced j 1752/3 with iec 61967-2 and updated data of table 51: emi data . removed note 3 related to accuracy of hsi oscillator. docid15590 rev 8 112/116 stm8s903k3 stm8s903f3 revision history
changes revision date updated ja in table 15: stm8s903k3 alternate function remapping bits [1:0] for 32-pin packages . changed ja to 60c/w in selecting the product temperature range section. ordering information : replaced package pitch digit by vfqfpn/ufqfpn package, and added footnote regarding possible future release of a dedicated ordering information scheme. added so20w, tssop20, sdip32, and ufqfpn32. added stm8s903k3/f3 fastrom microcontroller option list . modified p d at t a = 85 c for so20w in table 21: general operating conditions . 4 30-apr-2010 removed vfqfpn32 package. 5 08-sep-2010 updated "reset state" of table 4: legend/abbreviations for pinout tables in pinout and pin description . table 5: tssop20/so20/ufqfpn20 pin description : updated pins 13/25/20, 14/26/21, 19/32/27, 1/2/29, 2/3/30, and 3/4/31; added footnote to pd1/swim pin. general hardware register map : standardized all reset state values; updated the reset state values of rst_sr, clk_swcr, clk_hsitrimr, clk_swimccr, iwdg_kr, and adc_drx registers in the "general hardware register map" table. changed title of table 13: stm8s903k3 alternate function remapping bits [7:2] for 32-pin packages . added table 14: stm8s903f3 alternate function remapping bits [7:2] for 20-pin packages . changed title of table 15: stm8s903k3 alternate function remapping bits [1:0] for 32-pin packages . added table 16: stm8s903f3 alternate function remapping bits [1:0] for 20-pin packages . reset pin characteristics : replaced 0.01 f with 0.1 f in the "recommended reset pin protection" diagram. added #unique_58/title_4b4d811961b64279b556edc351811802 updated footnote 1 in table 48: adc accuracy with rain < 10 k , vdd= 5 v and table 49: adc accuracy with rain < 10 k rain, vdd = 3.3 v . #unique_77/cd14 : updated existing footnote and added three additional footnotes. 113/116 docid15590 rev 8 revision history stm8s903k3 stm8s903f3
changes revision date updated "special marking" and "opt2 alternate function remapping" sections in the stm8s903k3/f3 fastrom microcontroller option list . added note for opt1 option list. 6 28-jul-2011 updated opt2 option list for stm8s903k3 and created opt2 option list for stm8s903f3 in stm8s903k3/f3 fastrom microcontroller option list . updated uart1 interrupt vector addresses in table table 10: interrupt mapping updated note related to true open-drain outputs in table 5: tssop20/so20/ufqfpn20 pin description and table 5: tssop20/so20/ufqfpn20 pin description . added ufqfpn20 package. remove clk_canccr register from table 8: general hardware register map . added note for px_idr registers in table 7: i/o port hardware register map . updated title of ordering information . removed typical hsi accuracy curve in high speed internal rc oscillator (hsi) . updated value of recommended external capacitor to 100 nf in reset pin characteristics . updated disclaimer. internal reference voltage renamed internal bandgap reference voltage. 7 04-apr-2012 updated notes related to v cap in table 21: general operating conditions . added values of t r /t f for 50 pf load capacitance, and updated note in table 40: i/o static characteristics . updated typical and maximum values of r pu in table 40: i/o static characteristics and table 44: nrst pin characteristics . changed sck input to sck output in spi serial peripheral interface modified figure 47: 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) to add package top view. restored figure 44: typical application with adc 8 13-jun-2012 docid15590 rev 8 114/116 stm8s903k3 stm8s903f3 revision history
changes revision date modified figure 47: 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) to add package top view. 115/116 docid15590 rev 8 revision history stm8s903k3 stm8s903f3
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